63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
87 #define CLE_BPM_SERDES_CMD    0
91 	BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
199 	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 	mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
219 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
231 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
310 	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 	mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
331 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
341 	mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 	mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
362 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
372 	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 	mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
393 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
405 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 	mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
419 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
434 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
473 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 	mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
493 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
505 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
573 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 	mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 	mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
589 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
601 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
680 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
694 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 	mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
706 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 	mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 	mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
733 #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK                    0x0000007fL
734 #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT                  0x00000000L
801 		data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;  in gfx_v8_0_init_golden_registers()
803 		if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&  in gfx_v8_0_init_golden_registers()
804 		    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||  in gfx_v8_0_init_golden_registers()
805 		     (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||  in gfx_v8_0_init_golden_registers()
806 		     (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {  in gfx_v8_0_init_golden_registers()
807 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);  in gfx_v8_0_init_golden_registers()
808 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);  in gfx_v8_0_init_golden_registers()
841 	uint32_t tmp = 0;  in gfx_v8_0_ring_test_ring()
845 	WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);  in gfx_v8_0_ring_test_ring()
852 	amdgpu_ring_write(ring, 0xDEADBEEF);  in gfx_v8_0_ring_test_ring()
855 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_ring_test_ring()
857 		if (tmp == 0xDEADBEEF)  in gfx_v8_0_ring_test_ring()
884 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);  in gfx_v8_0_ring_test_ib()
885 	memset(&ib, 0, sizeof(ib));  in gfx_v8_0_ring_test_ib()
891 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v8_0_ring_test_ib()
895 	ib.ptr[4] = 0xDEADBEEF;  in gfx_v8_0_ring_test_ib()
903 	if (r == 0) {  in gfx_v8_0_ring_test_ib()
906 	} else if (r < 0) {  in gfx_v8_0_ring_test_ib()
911 	if (tmp == 0xDEADBEEF)  in gfx_v8_0_ring_test_ib()
912 		r = 0;  in gfx_v8_0_ring_test_ib()
1094 	for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)  in gfx_v8_0_init_microcode()
1101 	for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)  in gfx_v8_0_init_microcode()
1148 			err = 0;  in gfx_v8_0_init_microcode()
1226 	u32 count = 0, i;  in gfx_v8_0_get_csb_buffer()
1235 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1239 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v8_0_get_csb_buffer()
1240 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v8_0_get_csb_buffer()
1249 				for (i = 0; i < ext->reg_count; i++)  in gfx_v8_0_get_csb_buffer()
1260 	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);  in gfx_v8_0_get_csb_buffer()
1261 	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);  in gfx_v8_0_get_csb_buffer()
1263 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1266 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_get_csb_buffer()
1267 	buffer[count++] = cpu_to_le32(0);  in gfx_v8_0_get_csb_buffer()
1302 	/* init spm vmid with 0xf */  in gfx_v8_0_rlc_init()
1304 		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);  in gfx_v8_0_rlc_init()
1306 	return 0;  in gfx_v8_0_rlc_init()
1320 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in gfx_v8_0_mec_init()
1338 		memset(hpd, 0, mec_hpd_size);  in gfx_v8_0_mec_init()
1344 	return 0;  in gfx_v8_0_mec_init()
1349 	0x7e000209, 0x7e020208,
1350 	0x7e040207, 0x7e060206,
1351 	0x7e080205, 0x7e0a0204,
1352 	0x7e0c0203, 0x7e0e0202,
1353 	0x7e100201, 0x7e120200,
1354 	0x7e140209, 0x7e160208,
1355 	0x7e180207, 0x7e1a0206,
1356 	0x7e1c0205, 0x7e1e0204,
1357 	0x7e200203, 0x7e220202,
1358 	0x7e240201, 0x7e260200,
1359 	0x7e280209, 0x7e2a0208,
1360 	0x7e2c0207, 0x7e2e0206,
1361 	0x7e300205, 0x7e320204,
1362 	0x7e340203, 0x7e360202,
1363 	0x7e380201, 0x7e3a0200,
1364 	0x7e3c0209, 0x7e3e0208,
1365 	0x7e400207, 0x7e420206,
1366 	0x7e440205, 0x7e460204,
1367 	0x7e480203, 0x7e4a0202,
1368 	0x7e4c0201, 0x7e4e0200,
1369 	0x7e500209, 0x7e520208,
1370 	0x7e540207, 0x7e560206,
1371 	0x7e580205, 0x7e5a0204,
1372 	0x7e5c0203, 0x7e5e0202,
1373 	0x7e600201, 0x7e620200,
1374 	0x7e640209, 0x7e660208,
1375 	0x7e680207, 0x7e6a0206,
1376 	0x7e6c0205, 0x7e6e0204,
1377 	0x7e700203, 0x7e720202,
1378 	0x7e740201, 0x7e760200,
1379 	0x7e780209, 0x7e7a0208,
1380 	0x7e7c0207, 0x7e7e0206,
1381 	0xbf8a0000, 0xbf810000,
1386 	0xbe8a0100, 0xbe8c0102,
1387 	0xbe8e0104, 0xbe900106,
1388 	0xbe920108, 0xbe940100,
1389 	0xbe960102, 0xbe980104,
1390 	0xbe9a0106, 0xbe9c0108,
1391 	0xbe9e0100, 0xbea00102,
1392 	0xbea20104, 0xbea40106,
1393 	0xbea60108, 0xbea80100,
1394 	0xbeaa0102, 0xbeac0104,
1395 	0xbeae0106, 0xbeb00108,
1396 	0xbeb20100, 0xbeb40102,
1397 	0xbeb60104, 0xbeb80106,
1398 	0xbeba0108, 0xbebc0100,
1399 	0xbebe0102, 0xbec00104,
1400 	0xbec20106, 0xbec40108,
1401 	0xbec60100, 0xbec80102,
1402 	0xbee60004, 0xbee70005,
1403 	0xbeea0006, 0xbeeb0007,
1404 	0xbee80008, 0xbee90009,
1405 	0xbefc0000, 0xbf8a0000,
1406 	0xbf810000, 0x00000000,
1411 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1412 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1416 	mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1418 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1419 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1420 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1421 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1422 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1423 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1424 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1425 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1426 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1427 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1432 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1433 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1437 	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1439 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1440 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1441 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1442 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1443 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1444 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1445 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1446 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1447 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1448 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1453 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1454 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1458 	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1460 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1461 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1462 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1463 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1464 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1465 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1466 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1467 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1468 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1469 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1503 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];  in gfx_v8_0_do_edc_gpr_workarounds()
1513 		return 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1517 		return 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1520 	WREG32(mmGB_EDC_MODE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1535 	memset(&ib, 0, sizeof(ib));  in gfx_v8_0_do_edc_gpr_workarounds()
1544 	for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1547 	for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1550 	/* init the ib length to 0 */  in gfx_v8_0_do_edc_gpr_workarounds()
1551 	ib.length_dw = 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1555 	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1573 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1576 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1581 	for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1599 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1602 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1607 	for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1625 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1628 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1650 	tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;  in gfx_v8_0_do_edc_gpr_workarounds()
1655 	for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1685 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1686 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1687 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1688 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1702 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1703 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1704 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1705 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1717 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1718 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1719 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1720 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1732 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1733 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1734 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1735 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1749 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1750 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1751 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1752 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1766 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1767 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1768 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1769 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1783 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1784 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1785 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1786 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1800 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1801 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1802 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1803 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1829 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map…  in gfx_v8_0_gpu_early_init()
1830 			dimm00_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1831 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map…  in gfx_v8_0_gpu_early_init()
1832 			dimm01_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1833 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map…  in gfx_v8_0_gpu_early_init()
1834 			dimm10_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1835 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map…  in gfx_v8_0_gpu_early_init()
1836 			dimm11_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1859 		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);  in gfx_v8_0_gpu_early_init()
1870 	return 0;  in gfx_v8_0_gpu_early_init()
1908 	return 0;  in gfx_v8_0_compute_ring_init()
1916 	int xcc_id = 0;  in gfx_v8_0_sw_init()
1994 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v8_0_sw_init()
2013 	ring_id = 0;  in gfx_v8_0_sw_init()
2014 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v8_0_sw_init()
2015 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v8_0_sw_init()
2016 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v8_0_sw_init()
2017 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,  in gfx_v8_0_sw_init()
2032 	r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0);  in gfx_v8_0_sw_init()
2043 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0);  in gfx_v8_0_sw_init()
2047 	adev->gfx.ce_ram_size = 0x8000;  in gfx_v8_0_sw_init()
2053 	return 0;  in gfx_v8_0_sw_init()
2061 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_sw_fini()
2063 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_sw_fini()
2066 	amdgpu_gfx_mqd_sw_fini(adev, 0);  in gfx_v8_0_sw_fini()
2067 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);  in gfx_v8_0_sw_fini()
2068 	amdgpu_gfx_kiq_fini(adev, 0);  in gfx_v8_0_sw_fini()
2083 	return 0;  in gfx_v8_0_sw_fini()
2096 	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2097 		modearray[reg_offset] = 0;  in gfx_v8_0_tiling_mode_table_init()
2099 	for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2100 		mod2array[reg_offset] = 0;  in gfx_v8_0_tiling_mode_table_init()
2104 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2207 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |  in gfx_v8_0_tiling_mode_table_init()
2264 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2269 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2276 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2399 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2456 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2459 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2465 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2588 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2645 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2648 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2655 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2778 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2848 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2851 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2857 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2980 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3050 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3053 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3059 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
3162 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3219 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3224 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3236 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
3339 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3396 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3401 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3415 	if (instance == 0xffffffff)  in gfx_v8_0_select_se_sh()
3416 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);  in gfx_v8_0_select_se_sh()
3418 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);  in gfx_v8_0_select_se_sh()
3420 	if (se_num == 0xffffffff)  in gfx_v8_0_select_se_sh()
3425 	if (sh_num == 0xffffffff)  in gfx_v8_0_select_se_sh()
3477 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3483 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3486 		*rconf |= 0x0;  in gfx_v8_0_raster_config()
3487 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3490 		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);  in gfx_v8_0_raster_config()
3507 	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;  in gfx_v8_0_write_harvested_raster_configs()
3508 	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;  in gfx_v8_0_write_harvested_raster_configs()
3516 	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||  in gfx_v8_0_write_harvested_raster_configs()
3520 		if (!se_mask[0] && !se_mask[1]) {  in gfx_v8_0_write_harvested_raster_configs()
3529 	for (se = 0; se < num_se; se++) {  in gfx_v8_0_write_harvested_raster_configs()
3595 		gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_write_harvested_raster_configs()
3601 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_write_harvested_raster_configs()
3608 	u32 raster_config = 0, raster_config_1 = 0;  in gfx_v8_0_setup_rb()
3609 	u32 active_rbs = 0;  in gfx_v8_0_setup_rb()
3615 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_setup_rb()
3616 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_setup_rb()
3617 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3623 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3644 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_setup_rb()
3645 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_setup_rb()
3646 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3657 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3661 #define DEFAULT_SH_MEM_BASES	(0x6000)
3678 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)  in gfx_v8_0_init_compute_vmid()
3679 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)  in gfx_v8_0_init_compute_vmid()
3680 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)  in gfx_v8_0_init_compute_vmid()
3693 		vi_srbm_select(adev, 0, 0, 0, i);  in gfx_v8_0_init_compute_vmid()
3697 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_init_compute_vmid()
3700 	vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_init_compute_vmid()
3706 		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);  in gfx_v8_0_init_compute_vmid()
3707 		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);  in gfx_v8_0_init_compute_vmid()
3708 		WREG32(amdgpu_gds_reg_offset[i].gws, 0);  in gfx_v8_0_init_compute_vmid()
3709 		WREG32(amdgpu_gds_reg_offset[i].oa, 0);  in gfx_v8_0_init_compute_vmid()
3724 		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);  in gfx_v8_0_init_gds_vmid()
3725 		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);  in gfx_v8_0_init_gds_vmid()
3726 		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);  in gfx_v8_0_init_gds_vmid()
3727 		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);  in gfx_v8_0_init_gds_vmid()
3739 		adev->gfx.config.double_offchip_lds_buf = 0;  in gfx_v8_0_config_init()
3749 	WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);  in gfx_v8_0_constants_init()
3761 	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,  in gfx_v8_0_constants_init()
3770 	for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {  in gfx_v8_0_constants_init()
3771 		vi_srbm_select(adev, 0, 0, 0, i);  in gfx_v8_0_constants_init()
3773 		if (i == 0) {  in gfx_v8_0_constants_init()
3774 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);  in gfx_v8_0_constants_init()
3779 			WREG32(mmSH_MEM_BASES, 0);  in gfx_v8_0_constants_init()
3781 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);  in gfx_v8_0_constants_init()
3791 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_constants_init()
3793 	vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_constants_init()
3804 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_constants_init()
3833 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_wait_for_rlc_serdes()
3834 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_wait_for_rlc_serdes()
3835 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3836 			for (k = 0; k < adev->usec_timeout; k++) {  in gfx_v8_0_wait_for_rlc_serdes()
3837 				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
3842 				gfx_v8_0_select_se_sh(adev, 0xffffffff,  in gfx_v8_0_wait_for_rlc_serdes()
3843 						      0xffffffff, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3851 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3858 	for (k = 0; k < adev->usec_timeout; k++) {  in gfx_v8_0_wait_for_rlc_serdes()
3859 		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
3870 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3871 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3872 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3873 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3885 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);  in gfx_v8_0_init_csb()
3912 		if (register_list_format[ind_offset] == 0xFFFFFFFF) {  in gfx_v8_0_parse_ind_reg_list()
3920 		for (indices = 0;  in gfx_v8_0_parse_ind_reg_list()
3943 	int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};  in gfx_v8_0_init_save_restore_list()
3944 	int indices_count = 0;  in gfx_v8_0_init_save_restore_list()
3945 	int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};  in gfx_v8_0_init_save_restore_list()
3946 	int offset_count = 0;  in gfx_v8_0_init_save_restore_list()
3968 	WREG32(mmRLC_SRM_ARAM_ADDR, 0);  in gfx_v8_0_init_save_restore_list()
3969 	for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)  in gfx_v8_0_init_save_restore_list()
3974 	for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)  in gfx_v8_0_init_save_restore_list()
3985 	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)  in gfx_v8_0_init_save_restore_list()
3992 	for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {  in gfx_v8_0_init_save_restore_list()
3993 		if (unique_indices[i] != 0) {  in gfx_v8_0_init_save_restore_list()
3994 			WREG32(temp + i, unique_indices[i] & 0x3FFFF);  in gfx_v8_0_init_save_restore_list()
4000 	return 0;  in gfx_v8_0_init_save_restore_list()
4012 	WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);  in gfx_v8_0_init_power_gating()
4014 	data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4015 	data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4016 	data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4017 	data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4020 	WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);  in gfx_v8_0_init_power_gating()
4021 	WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);  in gfx_v8_0_init_power_gating()
4028 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_up()
4034 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_down()
4039 	WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);  in cz_enable_cp_power_gating()
4065 	WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);  in gfx_v8_0_rlc_stop()
4076 	WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);  in gfx_v8_0_rlc_reset()
4095 		return 0;  in gfx_v8_0_rlc_resume()
4103 	return 0;  in gfx_v8_0_rlc_resume()
4111 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4112 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4113 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4125 	u32 count = 0;  in gfx_v8_0_get_csb_size()
4139 				return 0;  in gfx_v8_0_get_csb_size()
4154 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_start()
4161 	WREG32(mmCP_ENDIAN_SWAP, 0);  in gfx_v8_0_cp_gfx_start()
4173 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4177 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v8_0_cp_gfx_start()
4178 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v8_0_cp_gfx_start()
4188 				for (i = 0; i < ext->reg_count; i++)  in gfx_v8_0_cp_gfx_start()
4196 	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);  in gfx_v8_0_cp_gfx_start()
4197 	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);  in gfx_v8_0_cp_gfx_start()
4199 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4202 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_cp_gfx_start()
4203 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_cp_gfx_start()
4208 	amdgpu_ring_write(ring, 0x8000);  in gfx_v8_0_cp_gfx_start()
4209 	amdgpu_ring_write(ring, 0x8000);  in gfx_v8_0_cp_gfx_start()
4213 	return 0;  in gfx_v8_0_cp_gfx_start()
4228 						DOORBELL_HIT, 0);  in gfx_v8_0_set_cpg_door_bell()
4232 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);  in gfx_v8_0_set_cpg_door_bell()
4240 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,  in gfx_v8_0_set_cpg_door_bell()
4257 	WREG32(mmCP_RB_WPTR_DELAY, 0);  in gfx_v8_0_cp_gfx_resume()
4259 	/* set the RB to use vmid 0 */  in gfx_v8_0_cp_gfx_resume()
4260 	WREG32(mmCP_RB_VMID, 0);  in gfx_v8_0_cp_gfx_resume()
4263 	ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_resume()
4265 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v8_0_cp_gfx_resume()
4276 	ring->wptr = 0;  in gfx_v8_0_cp_gfx_resume()
4282 	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);  in gfx_v8_0_cp_gfx_resume()
4299 	return 0;  in gfx_v8_0_cp_gfx_resume()
4305 		WREG32(mmCP_MEC_CNTL, 0);  in gfx_v8_0_cp_compute_enable()
4308 		adev->gfx.kiq[0].ring.sched.ready = false;  in gfx_v8_0_cp_compute_enable()
4321 	tmp &= 0xffffff00;  in gfx_v8_0_kiq_setting()
4323 	WREG32(mmRLC_CP_SCHEDULERS, tmp | 0x80);  in gfx_v8_0_kiq_setting()
4328 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kiq_kcq_enable()
4329 	uint64_t queue_mask = 0;  in gfx_v8_0_kiq_kcq_enable()
4332 	for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {  in gfx_v8_0_kiq_kcq_enable()
4333 		if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))  in gfx_v8_0_kiq_kcq_enable()
4354 	amdgpu_ring_write(kiq_ring, 0);	/* vmid_mask:0 queue_type:0 (KIQ) */  in gfx_v8_0_kiq_kcq_enable()
4357 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */  in gfx_v8_0_kiq_kcq_enable()
4358 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */  in gfx_v8_0_kiq_kcq_enable()
4359 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx_v8_0_kiq_kcq_enable()
4360 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx_v8_0_kiq_kcq_enable()
4361 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kiq_kcq_enable()
4368 		/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/  in gfx_v8_0_kiq_kcq_enable()
4375 				  PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */  in gfx_v8_0_kiq_kcq_enable()
4384 	return 0;  in gfx_v8_0_kiq_kcq_enable()
4389 	int i, r = 0;  in gfx_v8_0_deactivate_hqd()
4393 		for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_deactivate_hqd()
4401 	WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);  in gfx_v8_0_deactivate_hqd()
4402 	WREG32(mmCP_HQD_PQ_RPTR, 0);  in gfx_v8_0_deactivate_hqd()
4403 	WREG32(mmCP_HQD_PQ_WPTR, 0);  in gfx_v8_0_deactivate_hqd()
4428 	mqd->header = 0xC0310800;  in gfx_v8_0_mqd_init()
4429 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v8_0_mqd_init()
4430 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v8_0_mqd_init()
4431 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v8_0_mqd_init()
4432 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v8_0_mqd_init()
4433 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v8_0_mqd_init()
4434 	mqd->compute_misc_reserved = 0x00000003;  in gfx_v8_0_mqd_init()
4454 			    ring->use_doorbell ? 1 : 0);  in gfx_v8_0_mqd_init()
4459 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4462 	/* set MQD vmid to 0 */  in gfx_v8_0_mqd_init()
4464 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v8_0_mqd_init()
4481 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);  in gfx_v8_0_mqd_init()
4482 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);  in gfx_v8_0_mqd_init()
4489 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4491 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4495 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4496 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4498 	tmp = 0;  in gfx_v8_0_mqd_init()
4508 					 DOORBELL_SOURCE, 0);  in gfx_v8_0_mqd_init()
4510 					 DOORBELL_HIT, 0);  in gfx_v8_0_mqd_init()
4516 	ring->wptr = 0;  in gfx_v8_0_mqd_init()
4521 	mqd->cp_hqd_vmid = 0;  in gfx_v8_0_mqd_init()
4524 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);  in gfx_v8_0_mqd_init()
4565 	return 0;  in gfx_v8_0_mqd_init()
4578 	WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);  in gfx_v8_0_mqd_commit()
4602 	return 0;  in gfx_v8_0_mqd_commit()
4614 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v8_0_kiq_init_queue()
4615 			memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4618 		ring->wptr = 0;  in gfx_v8_0_kiq_init_queue()
4621 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kiq_init_queue()
4623 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kiq_init_queue()
4626 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4627 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4628 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4632 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kiq_init_queue()
4635 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kiq_init_queue()
4638 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v8_0_kiq_init_queue()
4639 			memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4642 	return 0;  in gfx_v8_0_kiq_init_queue()
4649 	int mqd_idx = ring - &adev->gfx.compute_ring[0];  in gfx_v8_0_kcq_init_queue()
4652 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4653 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4654 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4656 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kcq_init_queue()
4658 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kcq_init_queue()
4668 		ring->wptr = 0;  in gfx_v8_0_kcq_init_queue()
4671 	return 0;  in gfx_v8_0_kcq_init_queue()
4689 	ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kiq_resume()
4692 	if (unlikely(r != 0))  in gfx_v8_0_kiq_resume()
4696 	if (unlikely(r != 0)) {  in gfx_v8_0_kiq_resume()
4705 	return 0;  in gfx_v8_0_kiq_resume()
4711 	int r = 0, i;  in gfx_v8_0_kcq_resume()
4715 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kcq_resume()
4719 		if (unlikely(r != 0))  in gfx_v8_0_kcq_resume()
4748 	ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_test_all_rings()
4753 	ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_cp_test_all_rings()
4758 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_cp_test_all_rings()
4763 	return 0;  in gfx_v8_0_cp_test_all_rings()
4791 	return 0;  in gfx_v8_0_cp_resume()
4820 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kcq_disable()
4826 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kcq_disable()
4830 		amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx_v8_0_kcq_disable()
4832 						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |  in gfx_v8_0_kcq_disable()
4833 						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |  in gfx_v8_0_kcq_disable()
4836 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4837 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4838 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4859 		|| RREG32(mmGRBM_STATUS2) != 0x8)  in gfx_v8_0_is_idle()
4869 	if (RREG32(mmGRBM_STATUS2) != 0x8)  in gfx_v8_0_rlc_is_idle()
4880 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_wait_for_rlc_idle()
4882 			return 0;  in gfx_v8_0_wait_for_rlc_idle()
4894 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_wait_for_idle()
4896 			return 0;  in gfx_v8_0_wait_for_idle()
4907 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v8_0_hw_fini()
4908 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v8_0_hw_fini()
4910 	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);  in gfx_v8_0_hw_fini()
4912 	amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);  in gfx_v8_0_hw_fini()
4919 		return 0;  in gfx_v8_0_hw_fini()
4922 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_hw_fini()
4931 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_hw_fini()
4933 	return 0;  in gfx_v8_0_hw_fini()
4949 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
5002 		adev->gfx.grbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
5003 		adev->gfx.srbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
5011 	u32 grbm_soft_reset = 0;  in gfx_v8_0_pre_soft_reset()
5015 		return 0;  in gfx_v8_0_pre_soft_reset()
5033 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_pre_soft_reset()
5037 			vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_pre_soft_reset()
5039 			vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_pre_soft_reset()
5046 	return 0;  in gfx_v8_0_pre_soft_reset()
5052 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in gfx_v8_0_soft_reset()
5057 		return 0;  in gfx_v8_0_soft_reset()
5073 		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in gfx_v8_0_soft_reset()
5087 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gfx_v8_0_soft_reset()
5100 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);  in gfx_v8_0_soft_reset()
5101 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);  in gfx_v8_0_soft_reset()
5108 	return 0;  in gfx_v8_0_soft_reset()
5114 	u32 grbm_soft_reset = 0;  in gfx_v8_0_post_soft_reset()
5118 		return 0;  in gfx_v8_0_post_soft_reset()
5128 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_post_soft_reset()
5132 			vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_post_soft_reset()
5134 			vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_post_soft_reset()
5149 	return 0;  in gfx_v8_0_post_soft_reset()
5180 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5181 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5183 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5188 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5189 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5191 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5196 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5197 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5199 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5204 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5205 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5207 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5238 	/* type 0 wave data */  in gfx_v8_0_read_wave_data()
5239 	dst[(*no_fields)++] = 0;  in gfx_v8_0_read_wave_data()
5266 		adev, simd, wave, 0,  in gfx_v8_0_read_wave_sgprs()
5293 	return 0;  in gfx_v8_0_early_init()
5301 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v8_0_late_init()
5305 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v8_0_late_init()
5314 	r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);  in gfx_v8_0_late_init()
5320 	r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);  in gfx_v8_0_late_init()
5328 	return 0;  in gfx_v8_0_late_init()
5338 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable, 0);  in gfx_v8_0_enable_gfx_static_mg_power_gating()
5340 	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_static_mg_power_gating()
5346 	WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5352 	WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);  in polaris11_enable_gfx_quick_mg_power_gating()
5358 	WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_cg_power_gating()
5364 	WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_pipeline_power_gating()
5391 		return 0;  in gfx_v8_0_set_powergating_state()
5397 		amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_set_powergating_state()
5451 		amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_set_powergating_state()
5452 	return 0;  in gfx_v8_0_set_powergating_state()
5461 		*flags = 0;  in gfx_v8_0_get_clockgating_state()
5502 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_send_serdes_cmd()
5504 	WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);  in gfx_v8_0_send_serdes_cmd()
5505 	WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);  in gfx_v8_0_send_serdes_cmd()
5533 		 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));  in gfx_v8_0_send_serdes_cmd()
5539 #define MSG_EXIT_RLC_SAFE_MODE      0
5540 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5541 #define RLC_GPR_REG2__REQ__SHIFT 0
5542 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5543 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5567 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_set_safe_mode()
5576 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_set_safe_mode()
5593 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_unset_safe_mode()
5678 			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);  in gfx_v8_0_update_medium_grain_clock_gating()
5685 			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);  in gfx_v8_0_update_medium_grain_clock_gating()
5694 		/* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */  in gfx_v8_0_update_medium_grain_clock_gating()
5828 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_update_gfx_clock_gating()
5844 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_update_gfx_clock_gating()
5845 	return 0;  in gfx_v8_0_update_gfx_clock_gating()
5851 	uint32_t msg_id, pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5852 	uint32_t pp_support_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5864 			pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5885 			pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5894 	return 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5901 	uint32_t msg_id, pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5902 	uint32_t pp_support_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5914 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5933 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5954 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5967 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5982 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5992 	return 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
6001 		return 0;  in gfx_v8_0_set_clockgating_state()
6022 	return 0;  in gfx_v8_0_set_clockgating_state()
6071 		reg_mem_engine = 0;  in gfx_v8_0_ring_emit_hdp_flush()
6085 	amdgpu_ring_write(ring, 0x20); /* poll interval */  in gfx_v8_0_ring_emit_hdp_flush()
6090 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6094 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6096 		EVENT_INDEX(0));  in gfx_v8_0_ring_emit_vgt_flush()
6105 	u32 header, control = 0;  in gfx_v8_0_ring_emit_ib_gfx()
6124 			  (2 << 0) |  in gfx_v8_0_ring_emit_ib_gfx()
6126 			  (ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_gfx()
6127 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_gfx()
6147 	 * GDS to 0 for this ring (me/pipe).  in gfx_v8_0_ring_emit_ib_compute()
6158 				(2 << 0) |  in gfx_v8_0_ring_emit_ib_compute()
6160 				(ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_compute()
6161 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_compute()
6181 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_gfx()
6182 	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |  in gfx_v8_0_ring_emit_fence_gfx()
6183 				DATA_SEL(1) | INT_SEL(0));  in gfx_v8_0_ring_emit_fence_gfx()
6195 				 (exec ? EOP_EXEC : 0)));  in gfx_v8_0_ring_emit_fence_gfx()
6196 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_gfx()
6197 	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |  in gfx_v8_0_ring_emit_fence_gfx()
6198 			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));  in gfx_v8_0_ring_emit_fence_gfx()
6214 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_pipeline_sync()
6215 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);  in gfx_v8_0_ring_emit_pipeline_sync()
6217 	amdgpu_ring_write(ring, 0xffffffff);  in gfx_v8_0_ring_emit_pipeline_sync()
6230 	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */  in gfx_v8_0_ring_emit_vm_flush()
6231 				 WAIT_REG_MEM_FUNCTION(0) |  /* always */  in gfx_v8_0_ring_emit_vm_flush()
6232 				 WAIT_REG_MEM_ENGINE(0))); /* me */  in gfx_v8_0_ring_emit_vm_flush()
6234 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_vm_flush()
6235 	amdgpu_ring_write(ring, 0); /* ref */  in gfx_v8_0_ring_emit_vm_flush()
6236 	amdgpu_ring_write(ring, 0); /* mask */  in gfx_v8_0_ring_emit_vm_flush()
6237 	amdgpu_ring_write(ring, 0x20); /* poll interval */  in gfx_v8_0_ring_emit_vm_flush()
6242 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v8_0_ring_emit_vm_flush()
6243 		amdgpu_ring_write(ring, 0x0);  in gfx_v8_0_ring_emit_vm_flush()
6275 	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));  in gfx_v8_0_ring_emit_fence_compute()
6276 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_compute()
6290 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_fence_kiq()
6299 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_fence_kiq()
6300 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));  in gfx_v8_0_ring_emit_fence_kiq()
6302 		amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_fence_kiq()
6303 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */  in gfx_v8_0_ring_emit_fence_kiq()
6309 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v8_ring_emit_sb()
6310 	amdgpu_ring_write(ring, 0);  in gfx_v8_ring_emit_sb()
6315 	uint32_t dw2 = 0;  in gfx_v8_ring_emit_cntxcntl()
6320 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */  in gfx_v8_ring_emit_cntxcntl()
6324 		dw2 |= 0x8001;  in gfx_v8_ring_emit_cntxcntl()
6326 		dw2 |= 0x01000000;  in gfx_v8_ring_emit_cntxcntl()
6328 		dw2 |= 0x10002;  in gfx_v8_ring_emit_cntxcntl()
6332 			dw2 |= 0x10000000;  in gfx_v8_ring_emit_cntxcntl()
6338 			dw2 |= 0x10000000;  in gfx_v8_ring_emit_cntxcntl()
6343 	amdgpu_ring_write(ring, 0);  in gfx_v8_ring_emit_cntxcntl()
6354 	/* discard following DWs if *cond_exec_gpu_addr==0 */  in gfx_v8_0_ring_emit_init_cond_exec()
6355 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_init_cond_exec()
6358 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_init_cond_exec()
6368 	amdgpu_ring_write(ring, 0 |	/* src: register*/  in gfx_v8_0_ring_emit_rreg()
6372 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_rreg()
6399 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_wreg()
6410 			  /* memory (1) or register (0) */  in gfx_v8_0_wait_reg_mem()
6417 		BUG_ON(addr0 & 0x3); /* Dword align */  in gfx_v8_0_wait_reg_mem()
6428 	gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);  in gfx_v8_0_ring_emit_reg_wait()
6434 	uint32_t value = 0;  in gfx_v8_0_ring_soft_recovery()
6436 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);  in gfx_v8_0_ring_soft_recovery()
6437 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);  in gfx_v8_0_ring_soft_recovery()
6447 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_gfx_eop_interrupt_state()
6464 		case 0:  in gfx_v8_0_set_compute_eop_interrupt_state()
6507 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_priv_reg_fault_state()
6509 	return 0;  in gfx_v8_0_set_priv_reg_fault_state()
6518 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_priv_inst_fault_state()
6520 	return 0;  in gfx_v8_0_set_priv_inst_fault_state()
6533 		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);  in gfx_v8_0_set_eop_interrupt_state()
6545 		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);  in gfx_v8_0_set_eop_interrupt_state()
6559 	return 0;  in gfx_v8_0_set_eop_interrupt_state()
6571 		enable_flag = 0;  in gfx_v8_0_set_cp_ecc_int_state()
6604 	return 0;  in gfx_v8_0_set_cp_ecc_int_state()
6620 		enable_flag = 0;  in gfx_v8_0_set_sq_int_state()
6630 	return 0;  in gfx_v8_0_set_sq_int_state()
6642 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v8_0_eop_irq()
6643 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v8_0_eop_irq()
6644 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v8_0_eop_irq()
6647 	case 0:  in gfx_v8_0_eop_irq()
6648 		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v8_0_eop_irq()
6652 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_eop_irq()
6662 	return 0;  in gfx_v8_0_eop_irq()
6672 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v8_0_fault()
6673 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v8_0_fault()
6674 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v8_0_fault()
6677 	case 0:  in gfx_v8_0_fault()
6678 		drm_sched_fault(&adev->gfx.gfx_ring[0].sched);  in gfx_v8_0_fault()
6682 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_fault()
6698 	return 0;  in gfx_v8_0_priv_reg_irq()
6707 	return 0;  in gfx_v8_0_priv_inst_irq()
6715 	return 0;  in gfx_v8_0_cp_ecc_error_irq()
6729 		case 0:  in gfx_v8_0_parse_sq_irq()
6759 				gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0);  in gfx_v8_0_parse_sq_irq()
6763 				gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_parse_sq_irq()
6802 	unsigned ih_data = entry->src_data[0];  in gfx_v8_0_sq_irq()
6816 	return 0;  in gfx_v8_0_sq_irq()
6827 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */  in gfx_v8_0_emit_mem_sync()
6828 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE */  in gfx_v8_0_emit_mem_sync()
6829 	amdgpu_ring_write(ring, 0x0000000A); /* poll interval */  in gfx_v8_0_emit_mem_sync()
6840 	amdgpu_ring_write(ring, 0xffffffff);	/* CP_COHER_SIZE */  in gfx_v8_0_emit_mem_sync_compute()
6841 	amdgpu_ring_write(ring, 0xff);		/* CP_COHER_SIZE_HI */  in gfx_v8_0_emit_mem_sync_compute()
6842 	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE */  in gfx_v8_0_emit_mem_sync_compute()
6843 	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE_HI */  in gfx_v8_0_emit_mem_sync_compute()
6844 	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */  in gfx_v8_0_emit_mem_sync_compute()
6848 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6849 #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT	0x0000007f
6856 	val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;  in gfx_v8_0_emit_wave_limit_cs()
6859 	case 0:  in gfx_v8_0_emit_wave_limit_cs()
6880 #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT	0x07ffffff
6891 	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;  in gfx_v8_0_emit_wave_limit()
6897 	 * amdgpu controls only 1st ME(0-3 CS pipes).  in gfx_v8_0_emit_wave_limit()
6899 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v8_0_emit_wave_limit()
6910 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in gfx_v8_0_reset_kgq()
6929 	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);  in gfx_v8_0_reset_kgq()
6943 	gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);  in gfx_v8_0_reset_kgq()
6944 	gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);  in gfx_v8_0_reset_kgq()
6972 	.align_mask = 0xff,
6973 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7019 	.align_mask = 0xff,
7020 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7054 	.align_mask = 0xff,
7055 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7080 	adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq;  in gfx_v8_0_set_ring_funcs()
7082 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_set_ring_funcs()
7085 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_set_ring_funcs()
7174 	int i, j, k, counter, active_cu_number = 0;  in gfx_v8_0_get_cu_info()
7175 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;  in gfx_v8_0_get_cu_info()
7180 	memset(cu_info, 0, sizeof(*cu_info));  in gfx_v8_0_get_cu_info()
7190 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_get_cu_info()
7191 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_get_cu_info()
7193 			ao_bitmap = 0;  in gfx_v8_0_get_cu_info()
7194 			counter = 0;  in gfx_v8_0_get_cu_info()
7195 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_get_cu_info()
7200 			cu_info->bitmap[0][i][j] = bitmap;  in gfx_v8_0_get_cu_info()
7202 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {  in gfx_v8_0_get_cu_info()
7216 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_get_cu_info()
7232 	.minor = 0,
7233 	.rev = 0,
7242 	.rev = 0,
7269 				WRITE_DATA_CACHE_POLICY(0));  in gfx_v8_0_ring_emit_ce_meta()
7302 				WRITE_DATA_CACHE_POLICY(0));  in gfx_v8_0_ring_emit_de_meta()