63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK            0x00000001L
79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK            0x00000002L
80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK           0x00000004L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK           0x00000008L
82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK           0x00000010L
83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK           0x00000020L
87 #define CLE_BPM_SERDES_CMD    0
91 	BPM_REG_CGLS_EN = 0,        /* Enable/Disable CGLS */
199 	mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 	mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
219 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
231 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
310 	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 	mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
331 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
341 	mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 	mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
362 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
372 	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 	mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 	mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 	mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 	mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
393 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
405 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 	mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
419 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 	mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
434 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
473 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 	mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 	mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 	mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 	mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
493 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
505 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
573 	mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 	mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 	mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 	mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
589 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 	mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
601 	mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 	mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 	mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 	mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 	mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 	mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 	mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 	mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 	mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 	mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 	mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 	mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 	mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 	mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 	mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 	mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 	mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 	mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 	mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 	mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 	mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 	mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 	mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 	mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 	mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 	mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 	mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 	mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 	mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 	mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 	mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 	mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 	mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 	mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 	mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 	mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 	mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 	mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 	mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 	mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 	mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 	mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 	mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 	mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 	mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 	mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 	mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 	mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 	mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 	mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 	mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 	mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 	mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 	mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 	mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 	mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 	mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 	mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 	mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 	mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 	mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 	mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 	mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 	mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 	mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 	mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 	mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 	mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 	mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 	mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
680 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 	mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 	mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 	mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 	mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 	mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 	mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 	mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 	mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
694 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 	mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 	mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 	mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 	mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 	mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
706 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 	mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 	mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 	mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 	mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
733 #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK                    0x0000007fL
734 #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT                  0x00000000L
801 		data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;  in gfx_v8_0_init_golden_registers()
803 		if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&  in gfx_v8_0_init_golden_registers()
804 		    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||  in gfx_v8_0_init_golden_registers()
805 		     (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||  in gfx_v8_0_init_golden_registers()
806 		     (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {  in gfx_v8_0_init_golden_registers()
807 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);  in gfx_v8_0_init_golden_registers()
808 			amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);  in gfx_v8_0_init_golden_registers()
841 	uint32_t tmp = 0;  in gfx_v8_0_ring_test_ring()
845 	WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);  in gfx_v8_0_ring_test_ring()
852 	amdgpu_ring_write(ring, 0xDEADBEEF);  in gfx_v8_0_ring_test_ring()
855 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_ring_test_ring()
857 		if (tmp == 0xDEADBEEF)  in gfx_v8_0_ring_test_ring()
884 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);  in gfx_v8_0_ring_test_ib()
885 	memset(&ib, 0, sizeof(ib));  in gfx_v8_0_ring_test_ib()
891 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v8_0_ring_test_ib()
895 	ib.ptr[4] = 0xDEADBEEF;  in gfx_v8_0_ring_test_ib()
903 	if (r == 0) {  in gfx_v8_0_ring_test_ib()
906 	} else if (r < 0) {  in gfx_v8_0_ring_test_ib()
911 	if (tmp == 0xDEADBEEF)  in gfx_v8_0_ring_test_ib()
912 		r = 0;  in gfx_v8_0_ring_test_ib()
1084 	for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)  in gfx_v8_0_init_microcode()
1091 	for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)  in gfx_v8_0_init_microcode()
1132 			err = 0;  in gfx_v8_0_init_microcode()
1210 	u32 count = 0, i;  in gfx_v8_0_get_csb_buffer()
1219 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1223 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v8_0_get_csb_buffer()
1224 	buffer[count++] = cpu_to_le32(0x80000000);  in gfx_v8_0_get_csb_buffer()
1233 				for (i = 0; i < ext->reg_count; i++)  in gfx_v8_0_get_csb_buffer()
1244 	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);  in gfx_v8_0_get_csb_buffer()
1245 	buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);  in gfx_v8_0_get_csb_buffer()
1247 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1250 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_get_csb_buffer()
1251 	buffer[count++] = cpu_to_le32(0);  in gfx_v8_0_get_csb_buffer()
1286 	/* init spm vmid with 0xf */  in gfx_v8_0_rlc_init()
1288 		adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);  in gfx_v8_0_rlc_init()
1290 	return 0;  in gfx_v8_0_rlc_init()
1304 	bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);  in gfx_v8_0_mec_init()
1322 		memset(hpd, 0, mec_hpd_size);  in gfx_v8_0_mec_init()
1328 	return 0;  in gfx_v8_0_mec_init()
1333 	0x7e000209, 0x7e020208,
1334 	0x7e040207, 0x7e060206,
1335 	0x7e080205, 0x7e0a0204,
1336 	0x7e0c0203, 0x7e0e0202,
1337 	0x7e100201, 0x7e120200,
1338 	0x7e140209, 0x7e160208,
1339 	0x7e180207, 0x7e1a0206,
1340 	0x7e1c0205, 0x7e1e0204,
1341 	0x7e200203, 0x7e220202,
1342 	0x7e240201, 0x7e260200,
1343 	0x7e280209, 0x7e2a0208,
1344 	0x7e2c0207, 0x7e2e0206,
1345 	0x7e300205, 0x7e320204,
1346 	0x7e340203, 0x7e360202,
1347 	0x7e380201, 0x7e3a0200,
1348 	0x7e3c0209, 0x7e3e0208,
1349 	0x7e400207, 0x7e420206,
1350 	0x7e440205, 0x7e460204,
1351 	0x7e480203, 0x7e4a0202,
1352 	0x7e4c0201, 0x7e4e0200,
1353 	0x7e500209, 0x7e520208,
1354 	0x7e540207, 0x7e560206,
1355 	0x7e580205, 0x7e5a0204,
1356 	0x7e5c0203, 0x7e5e0202,
1357 	0x7e600201, 0x7e620200,
1358 	0x7e640209, 0x7e660208,
1359 	0x7e680207, 0x7e6a0206,
1360 	0x7e6c0205, 0x7e6e0204,
1361 	0x7e700203, 0x7e720202,
1362 	0x7e740201, 0x7e760200,
1363 	0x7e780209, 0x7e7a0208,
1364 	0x7e7c0207, 0x7e7e0206,
1365 	0xbf8a0000, 0xbf810000,
1370 	0xbe8a0100, 0xbe8c0102,
1371 	0xbe8e0104, 0xbe900106,
1372 	0xbe920108, 0xbe940100,
1373 	0xbe960102, 0xbe980104,
1374 	0xbe9a0106, 0xbe9c0108,
1375 	0xbe9e0100, 0xbea00102,
1376 	0xbea20104, 0xbea40106,
1377 	0xbea60108, 0xbea80100,
1378 	0xbeaa0102, 0xbeac0104,
1379 	0xbeae0106, 0xbeb00108,
1380 	0xbeb20100, 0xbeb40102,
1381 	0xbeb60104, 0xbeb80106,
1382 	0xbeba0108, 0xbebc0100,
1383 	0xbebe0102, 0xbec00104,
1384 	0xbec20106, 0xbec40108,
1385 	0xbec60100, 0xbec80102,
1386 	0xbee60004, 0xbee70005,
1387 	0xbeea0006, 0xbeeb0007,
1388 	0xbee80008, 0xbee90009,
1389 	0xbefc0000, 0xbf8a0000,
1390 	0xbf810000, 0x00000000,
1395 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1396 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1400 	mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1402 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1403 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1404 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1405 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1406 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1407 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1408 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1409 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1410 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1411 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1416 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1417 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1421 	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1423 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1424 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1425 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1426 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1427 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1428 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1429 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1430 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1431 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1432 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1437 	mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1438 	mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1442 	mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1444 	mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1445 	mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1446 	mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1447 	mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1448 	mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1449 	mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1450 	mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1451 	mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1452 	mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1453 	mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1487 	struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];  in gfx_v8_0_do_edc_gpr_workarounds()
1497 		return 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1501 		return 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1504 	WREG32(mmGB_EDC_MODE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1519 	memset(&ib, 0, sizeof(ib));  in gfx_v8_0_do_edc_gpr_workarounds()
1528 	for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1531 	for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1534 	/* init the ib length to 0 */  in gfx_v8_0_do_edc_gpr_workarounds()
1535 	ib.length_dw = 0;  in gfx_v8_0_do_edc_gpr_workarounds()
1539 	for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1557 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1560 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1565 	for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1583 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1586 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1591 	for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {  in gfx_v8_0_do_edc_gpr_workarounds()
1609 		REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1612 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1634 	tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;  in gfx_v8_0_do_edc_gpr_workarounds()
1639 	for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)  in gfx_v8_0_do_edc_gpr_workarounds()
1669 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1670 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1671 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1672 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1686 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1687 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1688 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1689 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1701 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1702 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1703 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1704 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1716 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1717 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1718 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1719 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1733 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1734 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1735 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1736 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1750 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1751 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1752 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1753 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1767 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1768 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1769 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1770 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1784 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1785 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1786 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1787 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1813 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map…  in gfx_v8_0_gpu_early_init()
1814 			dimm00_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1815 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map…  in gfx_v8_0_gpu_early_init()
1816 			dimm01_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1817 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map…  in gfx_v8_0_gpu_early_init()
1818 			dimm10_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1819 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map…  in gfx_v8_0_gpu_early_init()
1820 			dimm11_addr_map = 0;  in gfx_v8_0_gpu_early_init()
1843 		gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);  in gfx_v8_0_gpu_early_init()
1854 	return 0;  in gfx_v8_0_gpu_early_init()
1892 	return 0;  in gfx_v8_0_compute_ring_init()
1900 	int xcc_id = 0;  in gfx_v8_0_sw_init()
1978 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v8_0_sw_init()
1997 	ring_id = 0;  in gfx_v8_0_sw_init()
1998 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v8_0_sw_init()
1999 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v8_0_sw_init()
2000 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v8_0_sw_init()
2001 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,  in gfx_v8_0_sw_init()
2016 	r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0);  in gfx_v8_0_sw_init()
2027 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0);  in gfx_v8_0_sw_init()
2031 	adev->gfx.ce_ram_size = 0x8000;  in gfx_v8_0_sw_init()
2037 	return 0;  in gfx_v8_0_sw_init()
2045 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_sw_fini()
2047 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_sw_fini()
2050 	amdgpu_gfx_mqd_sw_fini(adev, 0);  in gfx_v8_0_sw_fini()
2051 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);  in gfx_v8_0_sw_fini()
2052 	amdgpu_gfx_kiq_fini(adev, 0);  in gfx_v8_0_sw_fini()
2067 	return 0;  in gfx_v8_0_sw_fini()
2080 	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2081 		modearray[reg_offset] = 0;  in gfx_v8_0_tiling_mode_table_init()
2083 	for (reg_offset = 0; reg_offset <  num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2084 		mod2array[reg_offset] = 0;  in gfx_v8_0_tiling_mode_table_init()
2088 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2191 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |  in gfx_v8_0_tiling_mode_table_init()
2248 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2253 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2260 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2383 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2440 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2443 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2449 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2572 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2629 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2632 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2639 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2762 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
2832 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2835 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
2841 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
2964 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3034 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3037 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3043 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
3146 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3203 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3208 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3220 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |  in gfx_v8_0_tiling_mode_table_init()
3323 		mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in gfx_v8_0_tiling_mode_table_init()
3380 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3385 		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)  in gfx_v8_0_tiling_mode_table_init()
3399 	if (instance == 0xffffffff)  in gfx_v8_0_select_se_sh()
3400 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);  in gfx_v8_0_select_se_sh()
3402 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);  in gfx_v8_0_select_se_sh()
3404 	if (se_num == 0xffffffff)  in gfx_v8_0_select_se_sh()
3409 	if (sh_num == 0xffffffff)  in gfx_v8_0_select_se_sh()
3461 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3467 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3470 		*rconf |= 0x0;  in gfx_v8_0_raster_config()
3471 		*rconf1 |= 0x0;  in gfx_v8_0_raster_config()
3474 		DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);  in gfx_v8_0_raster_config()
3491 	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;  in gfx_v8_0_write_harvested_raster_configs()
3492 	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;  in gfx_v8_0_write_harvested_raster_configs()
3500 	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||  in gfx_v8_0_write_harvested_raster_configs()
3504 		if (!se_mask[0] && !se_mask[1]) {  in gfx_v8_0_write_harvested_raster_configs()
3513 	for (se = 0; se < num_se; se++) {  in gfx_v8_0_write_harvested_raster_configs()
3579 		gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_write_harvested_raster_configs()
3585 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_write_harvested_raster_configs()
3592 	u32 raster_config = 0, raster_config_1 = 0;  in gfx_v8_0_setup_rb()
3593 	u32 active_rbs = 0;  in gfx_v8_0_setup_rb()
3599 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_setup_rb()
3600 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_setup_rb()
3601 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3607 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3628 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_setup_rb()
3629 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_setup_rb()
3630 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3641 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_setup_rb()
3645 #define DEFAULT_SH_MEM_BASES	(0x6000)
3662 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)  in gfx_v8_0_init_compute_vmid()
3663 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)  in gfx_v8_0_init_compute_vmid()
3664 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)  in gfx_v8_0_init_compute_vmid()
3677 		vi_srbm_select(adev, 0, 0, 0, i);  in gfx_v8_0_init_compute_vmid()
3681 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_init_compute_vmid()
3684 	vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_init_compute_vmid()
3690 		WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);  in gfx_v8_0_init_compute_vmid()
3691 		WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);  in gfx_v8_0_init_compute_vmid()
3692 		WREG32(amdgpu_gds_reg_offset[i].gws, 0);  in gfx_v8_0_init_compute_vmid()
3693 		WREG32(amdgpu_gds_reg_offset[i].oa, 0);  in gfx_v8_0_init_compute_vmid()
3708 		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);  in gfx_v8_0_init_gds_vmid()
3709 		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);  in gfx_v8_0_init_gds_vmid()
3710 		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);  in gfx_v8_0_init_gds_vmid()
3711 		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);  in gfx_v8_0_init_gds_vmid()
3723 		adev->gfx.config.double_offchip_lds_buf = 0;  in gfx_v8_0_config_init()
3733 	WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);  in gfx_v8_0_constants_init()
3745 	sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,  in gfx_v8_0_constants_init()
3754 	for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {  in gfx_v8_0_constants_init()
3755 		vi_srbm_select(adev, 0, 0, 0, i);  in gfx_v8_0_constants_init()
3757 		if (i == 0) {  in gfx_v8_0_constants_init()
3758 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);  in gfx_v8_0_constants_init()
3763 			WREG32(mmSH_MEM_BASES, 0);  in gfx_v8_0_constants_init()
3765 			tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);  in gfx_v8_0_constants_init()
3775 		WREG32(mmSH_MEM_APE1_LIMIT, 0);  in gfx_v8_0_constants_init()
3777 	vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_constants_init()
3788 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_constants_init()
3817 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_wait_for_rlc_serdes()
3818 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_wait_for_rlc_serdes()
3819 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3820 			for (k = 0; k < adev->usec_timeout; k++) {  in gfx_v8_0_wait_for_rlc_serdes()
3821 				if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
3826 				gfx_v8_0_select_se_sh(adev, 0xffffffff,  in gfx_v8_0_wait_for_rlc_serdes()
3827 						      0xffffffff, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3835 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_wait_for_rlc_serdes()
3842 	for (k = 0; k < adev->usec_timeout; k++) {  in gfx_v8_0_wait_for_rlc_serdes()
3843 		if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)  in gfx_v8_0_wait_for_rlc_serdes()
3854 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3855 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3856 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3857 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gui_idle_interrupt()
3869 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);  in gfx_v8_0_init_csb()
3896 		if (register_list_format[ind_offset] == 0xFFFFFFFF) {  in gfx_v8_0_parse_ind_reg_list()
3904 		for (indices = 0;  in gfx_v8_0_parse_ind_reg_list()
3927 	int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};  in gfx_v8_0_init_save_restore_list()
3928 	int indices_count = 0;  in gfx_v8_0_init_save_restore_list()
3929 	int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};  in gfx_v8_0_init_save_restore_list()
3930 	int offset_count = 0;  in gfx_v8_0_init_save_restore_list()
3952 	WREG32(mmRLC_SRM_ARAM_ADDR, 0);  in gfx_v8_0_init_save_restore_list()
3953 	for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)  in gfx_v8_0_init_save_restore_list()
3958 	for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)  in gfx_v8_0_init_save_restore_list()
3969 	for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)  in gfx_v8_0_init_save_restore_list()
3976 	for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {  in gfx_v8_0_init_save_restore_list()
3977 		if (unique_indices[i] != 0) {  in gfx_v8_0_init_save_restore_list()
3978 			WREG32(temp + i, unique_indices[i] & 0x3FFFF);  in gfx_v8_0_init_save_restore_list()
3984 	return 0;  in gfx_v8_0_init_save_restore_list()
3996 	WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);  in gfx_v8_0_init_power_gating()
3998 	data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
3999 	data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4000 	data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4001 	data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);  in gfx_v8_0_init_power_gating()
4004 	WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);  in gfx_v8_0_init_power_gating()
4005 	WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);  in gfx_v8_0_init_power_gating()
4012 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_up()
4018 	WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);  in cz_enable_sck_slow_down_on_power_down()
4023 	WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);  in cz_enable_cp_power_gating()
4049 	WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);  in gfx_v8_0_rlc_stop()
4060 	WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);  in gfx_v8_0_rlc_reset()
4079 		return 0;  in gfx_v8_0_rlc_resume()
4087 	return 0;  in gfx_v8_0_rlc_resume()
4095 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4096 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4097 		tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);  in gfx_v8_0_cp_gfx_enable()
4109 	u32 count = 0;  in gfx_v8_0_get_csb_size()
4123 				return 0;  in gfx_v8_0_get_csb_size()
4138 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_start()
4145 	WREG32(mmCP_ENDIAN_SWAP, 0);  in gfx_v8_0_cp_gfx_start()
4157 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4161 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v8_0_cp_gfx_start()
4162 	amdgpu_ring_write(ring, 0x80000000);  in gfx_v8_0_cp_gfx_start()
4172 				for (i = 0; i < ext->reg_count; i++)  in gfx_v8_0_cp_gfx_start()
4180 	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);  in gfx_v8_0_cp_gfx_start()
4181 	amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);  in gfx_v8_0_cp_gfx_start()
4183 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4186 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_cp_gfx_start()
4187 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_cp_gfx_start()
4192 	amdgpu_ring_write(ring, 0x8000);  in gfx_v8_0_cp_gfx_start()
4193 	amdgpu_ring_write(ring, 0x8000);  in gfx_v8_0_cp_gfx_start()
4197 	return 0;  in gfx_v8_0_cp_gfx_start()
4212 						DOORBELL_HIT, 0);  in gfx_v8_0_set_cpg_door_bell()
4216 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);  in gfx_v8_0_set_cpg_door_bell()
4224 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,  in gfx_v8_0_set_cpg_door_bell()
4241 	WREG32(mmCP_RB_WPTR_DELAY, 0);  in gfx_v8_0_cp_gfx_resume()
4243 	/* set the RB to use vmid 0 */  in gfx_v8_0_cp_gfx_resume()
4244 	WREG32(mmCP_RB_VMID, 0);  in gfx_v8_0_cp_gfx_resume()
4247 	ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_resume()
4249 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);  in gfx_v8_0_cp_gfx_resume()
4260 	ring->wptr = 0;  in gfx_v8_0_cp_gfx_resume()
4266 	WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);  in gfx_v8_0_cp_gfx_resume()
4283 	return 0;  in gfx_v8_0_cp_gfx_resume()
4289 		WREG32(mmCP_MEC_CNTL, 0);  in gfx_v8_0_cp_compute_enable()
4292 		adev->gfx.kiq[0].ring.sched.ready = false;  in gfx_v8_0_cp_compute_enable()
4305 	tmp &= 0xffffff00;  in gfx_v8_0_kiq_setting()
4308 	tmp |= 0x80;  in gfx_v8_0_kiq_setting()
4314 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kiq_kcq_enable()
4315 	uint64_t queue_mask = 0;  in gfx_v8_0_kiq_kcq_enable()
4318 	for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {  in gfx_v8_0_kiq_kcq_enable()
4319 		if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))  in gfx_v8_0_kiq_kcq_enable()
4340 	amdgpu_ring_write(kiq_ring, 0);	/* vmid_mask:0 queue_type:0 (KIQ) */  in gfx_v8_0_kiq_kcq_enable()
4343 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */  in gfx_v8_0_kiq_kcq_enable()
4344 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */  in gfx_v8_0_kiq_kcq_enable()
4345 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */  in gfx_v8_0_kiq_kcq_enable()
4346 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */  in gfx_v8_0_kiq_kcq_enable()
4347 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kiq_kcq_enable()
4354 		/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/  in gfx_v8_0_kiq_kcq_enable()
4361 				  PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */  in gfx_v8_0_kiq_kcq_enable()
4370 	return 0;  in gfx_v8_0_kiq_kcq_enable()
4375 	int i, r = 0;  in gfx_v8_0_deactivate_hqd()
4379 		for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_deactivate_hqd()
4387 	WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);  in gfx_v8_0_deactivate_hqd()
4388 	WREG32(mmCP_HQD_PQ_RPTR, 0);  in gfx_v8_0_deactivate_hqd()
4389 	WREG32(mmCP_HQD_PQ_WPTR, 0);  in gfx_v8_0_deactivate_hqd()
4414 	mqd->header = 0xC0310800;  in gfx_v8_0_mqd_init()
4415 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v8_0_mqd_init()
4416 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v8_0_mqd_init()
4417 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v8_0_mqd_init()
4418 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v8_0_mqd_init()
4419 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v8_0_mqd_init()
4420 	mqd->compute_misc_reserved = 0x00000003;  in gfx_v8_0_mqd_init()
4440 			    ring->use_doorbell ? 1 : 0);  in gfx_v8_0_mqd_init()
4445 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4448 	/* set MQD vmid to 0 */  in gfx_v8_0_mqd_init()
4450 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);  in gfx_v8_0_mqd_init()
4467 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);  in gfx_v8_0_mqd_init()
4468 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);  in gfx_v8_0_mqd_init()
4475 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4477 		upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4481 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4482 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4484 	tmp = 0;  in gfx_v8_0_mqd_init()
4494 					 DOORBELL_SOURCE, 0);  in gfx_v8_0_mqd_init()
4496 					 DOORBELL_HIT, 0);  in gfx_v8_0_mqd_init()
4502 	ring->wptr = 0;  in gfx_v8_0_mqd_init()
4507 	mqd->cp_hqd_vmid = 0;  in gfx_v8_0_mqd_init()
4510 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);  in gfx_v8_0_mqd_init()
4551 	return 0;  in gfx_v8_0_mqd_init()
4564 	WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);  in gfx_v8_0_mqd_commit()
4588 	return 0;  in gfx_v8_0_mqd_commit()
4600 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v8_0_kiq_init_queue()
4601 			memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4604 		ring->wptr = 0;  in gfx_v8_0_kiq_init_queue()
4607 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kiq_init_queue()
4609 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kiq_init_queue()
4612 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4613 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4614 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4618 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kiq_init_queue()
4621 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kiq_init_queue()
4624 		if (adev->gfx.kiq[0].mqd_backup)  in gfx_v8_0_kiq_init_queue()
4625 			memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4628 	return 0;  in gfx_v8_0_kiq_init_queue()
4635 	int mqd_idx = ring - &adev->gfx.compute_ring[0];  in gfx_v8_0_kcq_init_queue()
4638 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4639 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4640 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4642 		vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_kcq_init_queue()
4644 		vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_kcq_init_queue()
4654 		ring->wptr = 0;  in gfx_v8_0_kcq_init_queue()
4657 	return 0;  in gfx_v8_0_kcq_init_queue()
4675 	ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kiq_resume()
4678 	if (unlikely(r != 0))  in gfx_v8_0_kiq_resume()
4682 	if (unlikely(r != 0)) {  in gfx_v8_0_kiq_resume()
4691 	return 0;  in gfx_v8_0_kiq_resume()
4697 	int r = 0, i;  in gfx_v8_0_kcq_resume()
4701 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kcq_resume()
4705 		if (unlikely(r != 0))  in gfx_v8_0_kcq_resume()
4734 	ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_test_all_rings()
4739 	ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_cp_test_all_rings()
4744 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_cp_test_all_rings()
4749 	return 0;  in gfx_v8_0_cp_test_all_rings()
4777 	return 0;  in gfx_v8_0_cp_resume()
4806 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;  in gfx_v8_0_kcq_disable()
4812 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_kcq_disable()
4816 		amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */  in gfx_v8_0_kcq_disable()
4818 						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |  in gfx_v8_0_kcq_disable()
4819 						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |  in gfx_v8_0_kcq_disable()
4822 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4823 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4824 		amdgpu_ring_write(kiq_ring, 0);  in gfx_v8_0_kcq_disable()
4838 		|| RREG32(mmGRBM_STATUS2) != 0x8)  in gfx_v8_0_is_idle()
4848 	if (RREG32(mmGRBM_STATUS2) != 0x8)  in gfx_v8_0_rlc_is_idle()
4859 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_wait_for_rlc_idle()
4861 			return 0;  in gfx_v8_0_wait_for_rlc_idle()
4873 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_wait_for_idle()
4875 			return 0;  in gfx_v8_0_wait_for_idle()
4886 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v8_0_hw_fini()
4887 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v8_0_hw_fini()
4889 	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);  in gfx_v8_0_hw_fini()
4891 	amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);  in gfx_v8_0_hw_fini()
4898 		return 0;  in gfx_v8_0_hw_fini()
4900 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_hw_fini()
4909 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_hw_fini()
4911 	return 0;  in gfx_v8_0_hw_fini()
4927 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
4980 		adev->gfx.grbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
4981 		adev->gfx.srbm_soft_reset = 0;  in gfx_v8_0_check_soft_reset()
4989 	u32 grbm_soft_reset = 0;  in gfx_v8_0_pre_soft_reset()
4993 		return 0;  in gfx_v8_0_pre_soft_reset()
5011 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_pre_soft_reset()
5015 			vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_pre_soft_reset()
5017 			vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_pre_soft_reset()
5024 	return 0;  in gfx_v8_0_pre_soft_reset()
5030 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in gfx_v8_0_soft_reset()
5035 		return 0;  in gfx_v8_0_soft_reset()
5051 		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in gfx_v8_0_soft_reset()
5065 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gfx_v8_0_soft_reset()
5078 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);  in gfx_v8_0_soft_reset()
5079 		tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);  in gfx_v8_0_soft_reset()
5086 	return 0;  in gfx_v8_0_soft_reset()
5092 	u32 grbm_soft_reset = 0;  in gfx_v8_0_post_soft_reset()
5096 		return 0;  in gfx_v8_0_post_soft_reset()
5106 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_post_soft_reset()
5110 			vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);  in gfx_v8_0_post_soft_reset()
5112 			vi_srbm_select(adev, 0, 0, 0, 0);  in gfx_v8_0_post_soft_reset()
5127 	return 0;  in gfx_v8_0_post_soft_reset()
5158 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5159 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5161 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5166 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5167 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5169 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5174 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5175 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5177 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5182 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_gds_switch()
5183 				WRITE_DATA_DST_SEL(0)));  in gfx_v8_0_ring_emit_gds_switch()
5185 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_gds_switch()
5216 	/* type 0 wave data */  in gfx_v8_0_read_wave_data()
5217 	dst[(*no_fields)++] = 0;  in gfx_v8_0_read_wave_data()
5244 		adev, simd, wave, 0,  in gfx_v8_0_read_wave_sgprs()
5271 	return 0;  in gfx_v8_0_early_init()
5279 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);  in gfx_v8_0_late_init()
5283 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);  in gfx_v8_0_late_init()
5292 	r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);  in gfx_v8_0_late_init()
5298 	r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);  in gfx_v8_0_late_init()
5306 	return 0;  in gfx_v8_0_late_init()
5318 	WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_static_mg_power_gating()
5324 	WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);  in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5330 	WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);  in polaris11_enable_gfx_quick_mg_power_gating()
5336 	WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_cg_power_gating()
5342 	WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);  in cz_enable_gfx_pipeline_power_gating()
5369 		return 0;  in gfx_v8_0_set_powergating_state()
5375 		amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_set_powergating_state()
5429 		amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_set_powergating_state()
5430 	return 0;  in gfx_v8_0_set_powergating_state()
5439 		*flags = 0;  in gfx_v8_0_get_clockgating_state()
5480 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_send_serdes_cmd()
5482 	WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);  in gfx_v8_0_send_serdes_cmd()
5483 	WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);  in gfx_v8_0_send_serdes_cmd()
5511 		 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));  in gfx_v8_0_send_serdes_cmd()
5517 #define MSG_EXIT_RLC_SAFE_MODE      0
5518 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5519 #define RLC_GPR_REG2__REQ__SHIFT 0
5520 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5521 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5545 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_set_safe_mode()
5554 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_set_safe_mode()
5571 	for (i = 0; i < adev->usec_timeout; i++) {  in gfx_v8_0_unset_safe_mode()
5620 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_update_medium_grain_clock_gating()
5658 			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);  in gfx_v8_0_update_medium_grain_clock_gating()
5665 			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);  in gfx_v8_0_update_medium_grain_clock_gating()
5674 		/* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */  in gfx_v8_0_update_medium_grain_clock_gating()
5716 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_update_medium_grain_clock_gating()
5726 	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);  in gfx_v8_0_update_coarse_grain_clock_gating()
5809 	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);  in gfx_v8_0_update_coarse_grain_clock_gating()
5827 	return 0;  in gfx_v8_0_update_gfx_clock_gating()
5833 	uint32_t msg_id, pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5834 	uint32_t pp_support_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5846 			pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5867 			pp_state = 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5876 	return 0;  in gfx_v8_0_tonga_update_gfx_clock_gating()
5883 	uint32_t msg_id, pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5884 	uint32_t pp_support_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5896 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5915 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5936 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5949 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5964 			pp_state = 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5974 	return 0;  in gfx_v8_0_polaris_update_gfx_clock_gating()
5983 		return 0;  in gfx_v8_0_set_clockgating_state()
6004 	return 0;  in gfx_v8_0_set_clockgating_state()
6053 		reg_mem_engine = 0;  in gfx_v8_0_ring_emit_hdp_flush()
6067 	amdgpu_ring_write(ring, 0x20); /* poll interval */  in gfx_v8_0_ring_emit_hdp_flush()
6072 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6076 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6078 		EVENT_INDEX(0));  in gfx_v8_0_ring_emit_vgt_flush()
6087 	u32 header, control = 0;  in gfx_v8_0_ring_emit_ib_gfx()
6106 			  (2 << 0) |  in gfx_v8_0_ring_emit_ib_gfx()
6108 			  (ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_gfx()
6109 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_gfx()
6129 	 * GDS to 0 for this ring (me/pipe).  in gfx_v8_0_ring_emit_ib_compute()
6140 				(2 << 0) |  in gfx_v8_0_ring_emit_ib_compute()
6142 				(ib->gpu_addr & 0xFFFFFFFC));  in gfx_v8_0_ring_emit_ib_compute()
6143 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);  in gfx_v8_0_ring_emit_ib_compute()
6163 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_gfx()
6164 	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |  in gfx_v8_0_ring_emit_fence_gfx()
6165 				DATA_SEL(1) | INT_SEL(0));  in gfx_v8_0_ring_emit_fence_gfx()
6177 				 (exec ? EOP_EXEC : 0)));  in gfx_v8_0_ring_emit_fence_gfx()
6178 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_gfx()
6179 	amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |  in gfx_v8_0_ring_emit_fence_gfx()
6180 			  DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));  in gfx_v8_0_ring_emit_fence_gfx()
6196 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_pipeline_sync()
6197 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);  in gfx_v8_0_ring_emit_pipeline_sync()
6199 	amdgpu_ring_write(ring, 0xffffffff);  in gfx_v8_0_ring_emit_pipeline_sync()
6212 	amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */  in gfx_v8_0_ring_emit_vm_flush()
6213 				 WAIT_REG_MEM_FUNCTION(0) |  /* always */  in gfx_v8_0_ring_emit_vm_flush()
6214 				 WAIT_REG_MEM_ENGINE(0))); /* me */  in gfx_v8_0_ring_emit_vm_flush()
6216 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_vm_flush()
6217 	amdgpu_ring_write(ring, 0); /* ref */  in gfx_v8_0_ring_emit_vm_flush()
6218 	amdgpu_ring_write(ring, 0); /* mask */  in gfx_v8_0_ring_emit_vm_flush()
6219 	amdgpu_ring_write(ring, 0x20); /* poll interval */  in gfx_v8_0_ring_emit_vm_flush()
6224 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v8_0_ring_emit_vm_flush()
6225 		amdgpu_ring_write(ring, 0x0);  in gfx_v8_0_ring_emit_vm_flush()
6257 	amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));  in gfx_v8_0_ring_emit_fence_compute()
6258 	amdgpu_ring_write(ring, addr & 0xfffffffc);  in gfx_v8_0_ring_emit_fence_compute()
6272 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_fence_kiq()
6281 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |  in gfx_v8_0_ring_emit_fence_kiq()
6282 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));  in gfx_v8_0_ring_emit_fence_kiq()
6284 		amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_fence_kiq()
6285 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */  in gfx_v8_0_ring_emit_fence_kiq()
6291 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v8_ring_emit_sb()
6292 	amdgpu_ring_write(ring, 0);  in gfx_v8_ring_emit_sb()
6297 	uint32_t dw2 = 0;  in gfx_v8_ring_emit_cntxcntl()
6302 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */  in gfx_v8_ring_emit_cntxcntl()
6306 		dw2 |= 0x8001;  in gfx_v8_ring_emit_cntxcntl()
6308 		dw2 |= 0x01000000;  in gfx_v8_ring_emit_cntxcntl()
6310 		dw2 |= 0x10002;  in gfx_v8_ring_emit_cntxcntl()
6314 			dw2 |= 0x10000000;  in gfx_v8_ring_emit_cntxcntl()
6320 			dw2 |= 0x10000000;  in gfx_v8_ring_emit_cntxcntl()
6325 	amdgpu_ring_write(ring, 0);  in gfx_v8_ring_emit_cntxcntl()
6336 	/* discard following DWs if *cond_exec_gpu_addr==0 */  in gfx_v8_0_ring_emit_init_cond_exec()
6337 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_init_cond_exec()
6340 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_init_cond_exec()
6350 	amdgpu_ring_write(ring, 0 |	/* src: register*/  in gfx_v8_0_ring_emit_rreg()
6354 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_rreg()
6381 	amdgpu_ring_write(ring, 0);  in gfx_v8_0_ring_emit_wreg()
6392 			  /* memory (1) or register (0) */  in gfx_v8_0_wait_reg_mem()
6399 		BUG_ON(addr0 & 0x3); /* Dword align */  in gfx_v8_0_wait_reg_mem()
6410 	gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);  in gfx_v8_0_ring_emit_reg_wait()
6416 	uint32_t value = 0;  in gfx_v8_0_ring_soft_recovery()
6418 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);  in gfx_v8_0_ring_soft_recovery()
6419 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);  in gfx_v8_0_ring_soft_recovery()
6429 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_gfx_eop_interrupt_state()
6446 		case 0:  in gfx_v8_0_set_compute_eop_interrupt_state()
6489 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_priv_reg_fault_state()
6491 	return 0;  in gfx_v8_0_set_priv_reg_fault_state()
6500 		     state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);  in gfx_v8_0_set_priv_inst_fault_state()
6502 	return 0;  in gfx_v8_0_set_priv_inst_fault_state()
6515 		gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);  in gfx_v8_0_set_eop_interrupt_state()
6527 		gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);  in gfx_v8_0_set_eop_interrupt_state()
6541 	return 0;  in gfx_v8_0_set_eop_interrupt_state()
6553 		enable_flag = 0;  in gfx_v8_0_set_cp_ecc_int_state()
6586 	return 0;  in gfx_v8_0_set_cp_ecc_int_state()
6602 		enable_flag = 0;  in gfx_v8_0_set_sq_int_state()
6612 	return 0;  in gfx_v8_0_set_sq_int_state()
6624 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v8_0_eop_irq()
6625 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v8_0_eop_irq()
6626 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v8_0_eop_irq()
6629 	case 0:  in gfx_v8_0_eop_irq()
6630 		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v8_0_eop_irq()
6634 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_eop_irq()
6644 	return 0;  in gfx_v8_0_eop_irq()
6654 	me_id = (entry->ring_id & 0x0c) >> 2;  in gfx_v8_0_fault()
6655 	pipe_id = (entry->ring_id & 0x03) >> 0;  in gfx_v8_0_fault()
6656 	queue_id = (entry->ring_id & 0x70) >> 4;  in gfx_v8_0_fault()
6659 	case 0:  in gfx_v8_0_fault()
6660 		drm_sched_fault(&adev->gfx.gfx_ring[0].sched);  in gfx_v8_0_fault()
6664 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_fault()
6680 	return 0;  in gfx_v8_0_priv_reg_irq()
6689 	return 0;  in gfx_v8_0_priv_inst_irq()
6697 	return 0;  in gfx_v8_0_cp_ecc_error_irq()
6711 		case 0:  in gfx_v8_0_parse_sq_irq()
6741 				gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0);  in gfx_v8_0_parse_sq_irq()
6745 				gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_parse_sq_irq()
6784 	unsigned ih_data = entry->src_data[0];  in gfx_v8_0_sq_irq()
6798 	return 0;  in gfx_v8_0_sq_irq()
6809 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */  in gfx_v8_0_emit_mem_sync()
6810 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE */  in gfx_v8_0_emit_mem_sync()
6811 	amdgpu_ring_write(ring, 0x0000000A); /* poll interval */  in gfx_v8_0_emit_mem_sync()
6822 	amdgpu_ring_write(ring, 0xffffffff);	/* CP_COHER_SIZE */  in gfx_v8_0_emit_mem_sync_compute()
6823 	amdgpu_ring_write(ring, 0xff);		/* CP_COHER_SIZE_HI */  in gfx_v8_0_emit_mem_sync_compute()
6824 	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE */  in gfx_v8_0_emit_mem_sync_compute()
6825 	amdgpu_ring_write(ring, 0);		/* CP_COHER_BASE_HI */  in gfx_v8_0_emit_mem_sync_compute()
6826 	amdgpu_ring_write(ring, 0x0000000A);	/* poll interval */  in gfx_v8_0_emit_mem_sync_compute()
6830 /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6831 #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT	0x0000007f
6838 	val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;  in gfx_v8_0_emit_wave_limit_cs()
6841 	case 0:  in gfx_v8_0_emit_wave_limit_cs()
6862 #define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT	0x07ffffff
6873 	val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;  in gfx_v8_0_emit_wave_limit()
6879 	 * amdgpu controls only 1st ME(0-3 CS pipes).  in gfx_v8_0_emit_wave_limit()
6881 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {  in gfx_v8_0_emit_wave_limit()
6892 	struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];  in gfx_v8_0_reset_kgq()
6911 	tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);  in gfx_v8_0_reset_kgq()
6925 	gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);  in gfx_v8_0_reset_kgq()
6926 	gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);  in gfx_v8_0_reset_kgq()
6956 	.align_mask = 0xff,
6957 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7003 	.align_mask = 0xff,
7004 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7038 	.align_mask = 0xff,
7039 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7064 	adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq;  in gfx_v8_0_set_ring_funcs()
7066 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_set_ring_funcs()
7069 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_set_ring_funcs()
7158 	int i, j, k, counter, active_cu_number = 0;  in gfx_v8_0_get_cu_info()
7159 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;  in gfx_v8_0_get_cu_info()
7164 	memset(cu_info, 0, sizeof(*cu_info));  in gfx_v8_0_get_cu_info()
7174 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_get_cu_info()
7175 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_get_cu_info()
7177 			ao_bitmap = 0;  in gfx_v8_0_get_cu_info()
7178 			counter = 0;  in gfx_v8_0_get_cu_info()
7179 			gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);  in gfx_v8_0_get_cu_info()
7184 			cu_info->bitmap[0][i][j] = bitmap;  in gfx_v8_0_get_cu_info()
7186 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {  in gfx_v8_0_get_cu_info()
7200 	gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);  in gfx_v8_0_get_cu_info()
7216 	.minor = 0,
7217 	.rev = 0,
7226 	.rev = 0,
7253 				WRITE_DATA_CACHE_POLICY(0));  in gfx_v8_0_ring_emit_ce_meta()
7286 				WRITE_DATA_CACHE_POLICY(0));  in gfx_v8_0_ring_emit_de_meta()