2727 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);  in gfx_v7_0_mec_fini()
2742 	mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec  in gfx_v7_0_mec_init()
2748 				      &adev->gfx.mec.hpd_eop_obj,  in gfx_v7_0_mec_init()
2749 				      &adev->gfx.mec.hpd_eop_gpu_addr,  in gfx_v7_0_mec_init()
2760 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
2761 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v7_0_mec_init()
2767 				       int mec, int pipe)  in gfx_v7_0_compute_pipe_init()  argument
2771 	size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)  in gfx_v7_0_compute_pipe_init()
2775 	eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;  in gfx_v7_0_compute_pipe_init()
2777 	cik_srbm_select(adev, mec + 1, pipe, 0, 0);  in gfx_v7_0_compute_pipe_init()
3016 	for (i = 0; i < adev->gfx.mec.num_mec; i++)  in gfx_v7_0_cp_compute_resume()
3017 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)  in gfx_v7_0_cp_compute_resume()
4321 					int mec, int pipe, int queue)  in gfx_v7_0_compute_ring_init()  argument
4328 	ring->me = mec + 1;  in gfx_v7_0_compute_ring_init()
4338 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)  in gfx_v7_0_compute_ring_init()
4360 		adev->gfx.mec.num_mec = 2;  in gfx_v7_0_sw_init()
4367 		adev->gfx.mec.num_mec = 1;  in gfx_v7_0_sw_init()
4370 	adev->gfx.mec.num_pipe_per_mec = 4;  in gfx_v7_0_sw_init()
4371 	adev->gfx.mec.num_queue_per_pipe = 8;  in gfx_v7_0_sw_init()
4423 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v7_0_sw_init()
4424 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v7_0_sw_init()
4425 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v7_0_sw_init()