Lines Matching +full:0 +full:x8e00
53 #define NUM_SIMD_PER_CU 0x4 /* missing from the gfx_7 IP headers */
58 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
59 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
116 (0x0e00 << 16) | (0xc12c >> 2),
117 0x00000000,
118 (0x0e00 << 16) | (0xc140 >> 2),
119 0x00000000,
120 (0x0e00 << 16) | (0xc150 >> 2),
121 0x00000000,
122 (0x0e00 << 16) | (0xc15c >> 2),
123 0x00000000,
124 (0x0e00 << 16) | (0xc168 >> 2),
125 0x00000000,
126 (0x0e00 << 16) | (0xc170 >> 2),
127 0x00000000,
128 (0x0e00 << 16) | (0xc178 >> 2),
129 0x00000000,
130 (0x0e00 << 16) | (0xc204 >> 2),
131 0x00000000,
132 (0x0e00 << 16) | (0xc2b4 >> 2),
133 0x00000000,
134 (0x0e00 << 16) | (0xc2b8 >> 2),
135 0x00000000,
136 (0x0e00 << 16) | (0xc2bc >> 2),
137 0x00000000,
138 (0x0e00 << 16) | (0xc2c0 >> 2),
139 0x00000000,
140 (0x0e00 << 16) | (0x8228 >> 2),
141 0x00000000,
142 (0x0e00 << 16) | (0x829c >> 2),
143 0x00000000,
144 (0x0e00 << 16) | (0x869c >> 2),
145 0x00000000,
146 (0x0600 << 16) | (0x98f4 >> 2),
147 0x00000000,
148 (0x0e00 << 16) | (0x98f8 >> 2),
149 0x00000000,
150 (0x0e00 << 16) | (0x9900 >> 2),
151 0x00000000,
152 (0x0e00 << 16) | (0xc260 >> 2),
153 0x00000000,
154 (0x0e00 << 16) | (0x90e8 >> 2),
155 0x00000000,
156 (0x0e00 << 16) | (0x3c000 >> 2),
157 0x00000000,
158 (0x0e00 << 16) | (0x3c00c >> 2),
159 0x00000000,
160 (0x0e00 << 16) | (0x8c1c >> 2),
161 0x00000000,
162 (0x0e00 << 16) | (0x9700 >> 2),
163 0x00000000,
164 (0x0e00 << 16) | (0xcd20 >> 2),
165 0x00000000,
166 (0x4e00 << 16) | (0xcd20 >> 2),
167 0x00000000,
168 (0x5e00 << 16) | (0xcd20 >> 2),
169 0x00000000,
170 (0x6e00 << 16) | (0xcd20 >> 2),
171 0x00000000,
172 (0x7e00 << 16) | (0xcd20 >> 2),
173 0x00000000,
174 (0x8e00 << 16) | (0xcd20 >> 2),
175 0x00000000,
176 (0x9e00 << 16) | (0xcd20 >> 2),
177 0x00000000,
178 (0xae00 << 16) | (0xcd20 >> 2),
179 0x00000000,
180 (0xbe00 << 16) | (0xcd20 >> 2),
181 0x00000000,
182 (0x0e00 << 16) | (0x89bc >> 2),
183 0x00000000,
184 (0x0e00 << 16) | (0x8900 >> 2),
185 0x00000000,
186 0x3,
187 (0x0e00 << 16) | (0xc130 >> 2),
188 0x00000000,
189 (0x0e00 << 16) | (0xc134 >> 2),
190 0x00000000,
191 (0x0e00 << 16) | (0xc1fc >> 2),
192 0x00000000,
193 (0x0e00 << 16) | (0xc208 >> 2),
194 0x00000000,
195 (0x0e00 << 16) | (0xc264 >> 2),
196 0x00000000,
197 (0x0e00 << 16) | (0xc268 >> 2),
198 0x00000000,
199 (0x0e00 << 16) | (0xc26c >> 2),
200 0x00000000,
201 (0x0e00 << 16) | (0xc270 >> 2),
202 0x00000000,
203 (0x0e00 << 16) | (0xc274 >> 2),
204 0x00000000,
205 (0x0e00 << 16) | (0xc278 >> 2),
206 0x00000000,
207 (0x0e00 << 16) | (0xc27c >> 2),
208 0x00000000,
209 (0x0e00 << 16) | (0xc280 >> 2),
210 0x00000000,
211 (0x0e00 << 16) | (0xc284 >> 2),
212 0x00000000,
213 (0x0e00 << 16) | (0xc288 >> 2),
214 0x00000000,
215 (0x0e00 << 16) | (0xc28c >> 2),
216 0x00000000,
217 (0x0e00 << 16) | (0xc290 >> 2),
218 0x00000000,
219 (0x0e00 << 16) | (0xc294 >> 2),
220 0x00000000,
221 (0x0e00 << 16) | (0xc298 >> 2),
222 0x00000000,
223 (0x0e00 << 16) | (0xc29c >> 2),
224 0x00000000,
225 (0x0e00 << 16) | (0xc2a0 >> 2),
226 0x00000000,
227 (0x0e00 << 16) | (0xc2a4 >> 2),
228 0x00000000,
229 (0x0e00 << 16) | (0xc2a8 >> 2),
230 0x00000000,
231 (0x0e00 << 16) | (0xc2ac >> 2),
232 0x00000000,
233 (0x0e00 << 16) | (0xc2b0 >> 2),
234 0x00000000,
235 (0x0e00 << 16) | (0x301d0 >> 2),
236 0x00000000,
237 (0x0e00 << 16) | (0x30238 >> 2),
238 0x00000000,
239 (0x0e00 << 16) | (0x30250 >> 2),
240 0x00000000,
241 (0x0e00 << 16) | (0x30254 >> 2),
242 0x00000000,
243 (0x0e00 << 16) | (0x30258 >> 2),
244 0x00000000,
245 (0x0e00 << 16) | (0x3025c >> 2),
246 0x00000000,
247 (0x4e00 << 16) | (0xc900 >> 2),
248 0x00000000,
249 (0x5e00 << 16) | (0xc900 >> 2),
250 0x00000000,
251 (0x6e00 << 16) | (0xc900 >> 2),
252 0x00000000,
253 (0x7e00 << 16) | (0xc900 >> 2),
254 0x00000000,
255 (0x8e00 << 16) | (0xc900 >> 2),
256 0x00000000,
257 (0x9e00 << 16) | (0xc900 >> 2),
258 0x00000000,
259 (0xae00 << 16) | (0xc900 >> 2),
260 0x00000000,
261 (0xbe00 << 16) | (0xc900 >> 2),
262 0x00000000,
263 (0x4e00 << 16) | (0xc904 >> 2),
264 0x00000000,
265 (0x5e00 << 16) | (0xc904 >> 2),
266 0x00000000,
267 (0x6e00 << 16) | (0xc904 >> 2),
268 0x00000000,
269 (0x7e00 << 16) | (0xc904 >> 2),
270 0x00000000,
271 (0x8e00 << 16) | (0xc904 >> 2),
272 0x00000000,
273 (0x9e00 << 16) | (0xc904 >> 2),
274 0x00000000,
275 (0xae00 << 16) | (0xc904 >> 2),
276 0x00000000,
277 (0xbe00 << 16) | (0xc904 >> 2),
278 0x00000000,
279 (0x4e00 << 16) | (0xc908 >> 2),
280 0x00000000,
281 (0x5e00 << 16) | (0xc908 >> 2),
282 0x00000000,
283 (0x6e00 << 16) | (0xc908 >> 2),
284 0x00000000,
285 (0x7e00 << 16) | (0xc908 >> 2),
286 0x00000000,
287 (0x8e00 << 16) | (0xc908 >> 2),
288 0x00000000,
289 (0x9e00 << 16) | (0xc908 >> 2),
290 0x00000000,
291 (0xae00 << 16) | (0xc908 >> 2),
292 0x00000000,
293 (0xbe00 << 16) | (0xc908 >> 2),
294 0x00000000,
295 (0x4e00 << 16) | (0xc90c >> 2),
296 0x00000000,
297 (0x5e00 << 16) | (0xc90c >> 2),
298 0x00000000,
299 (0x6e00 << 16) | (0xc90c >> 2),
300 0x00000000,
301 (0x7e00 << 16) | (0xc90c >> 2),
302 0x00000000,
303 (0x8e00 << 16) | (0xc90c >> 2),
304 0x00000000,
305 (0x9e00 << 16) | (0xc90c >> 2),
306 0x00000000,
307 (0xae00 << 16) | (0xc90c >> 2),
308 0x00000000,
309 (0xbe00 << 16) | (0xc90c >> 2),
310 0x00000000,
311 (0x4e00 << 16) | (0xc910 >> 2),
312 0x00000000,
313 (0x5e00 << 16) | (0xc910 >> 2),
314 0x00000000,
315 (0x6e00 << 16) | (0xc910 >> 2),
316 0x00000000,
317 (0x7e00 << 16) | (0xc910 >> 2),
318 0x00000000,
319 (0x8e00 << 16) | (0xc910 >> 2),
320 0x00000000,
321 (0x9e00 << 16) | (0xc910 >> 2),
322 0x00000000,
323 (0xae00 << 16) | (0xc910 >> 2),
324 0x00000000,
325 (0xbe00 << 16) | (0xc910 >> 2),
326 0x00000000,
327 (0x0e00 << 16) | (0xc99c >> 2),
328 0x00000000,
329 (0x0e00 << 16) | (0x9834 >> 2),
330 0x00000000,
331 (0x0000 << 16) | (0x30f00 >> 2),
332 0x00000000,
333 (0x0001 << 16) | (0x30f00 >> 2),
334 0x00000000,
335 (0x0000 << 16) | (0x30f04 >> 2),
336 0x00000000,
337 (0x0001 << 16) | (0x30f04 >> 2),
338 0x00000000,
339 (0x0000 << 16) | (0x30f08 >> 2),
340 0x00000000,
341 (0x0001 << 16) | (0x30f08 >> 2),
342 0x00000000,
343 (0x0000 << 16) | (0x30f0c >> 2),
344 0x00000000,
345 (0x0001 << 16) | (0x30f0c >> 2),
346 0x00000000,
347 (0x0600 << 16) | (0x9b7c >> 2),
348 0x00000000,
349 (0x0e00 << 16) | (0x8a14 >> 2),
350 0x00000000,
351 (0x0e00 << 16) | (0x8a18 >> 2),
352 0x00000000,
353 (0x0600 << 16) | (0x30a00 >> 2),
354 0x00000000,
355 (0x0e00 << 16) | (0x8bf0 >> 2),
356 0x00000000,
357 (0x0e00 << 16) | (0x8bcc >> 2),
358 0x00000000,
359 (0x0e00 << 16) | (0x8b24 >> 2),
360 0x00000000,
361 (0x0e00 << 16) | (0x30a04 >> 2),
362 0x00000000,
363 (0x0600 << 16) | (0x30a10 >> 2),
364 0x00000000,
365 (0x0600 << 16) | (0x30a14 >> 2),
366 0x00000000,
367 (0x0600 << 16) | (0x30a18 >> 2),
368 0x00000000,
369 (0x0600 << 16) | (0x30a2c >> 2),
370 0x00000000,
371 (0x0e00 << 16) | (0xc700 >> 2),
372 0x00000000,
373 (0x0e00 << 16) | (0xc704 >> 2),
374 0x00000000,
375 (0x0e00 << 16) | (0xc708 >> 2),
376 0x00000000,
377 (0x0e00 << 16) | (0xc768 >> 2),
378 0x00000000,
379 (0x0400 << 16) | (0xc770 >> 2),
380 0x00000000,
381 (0x0400 << 16) | (0xc774 >> 2),
382 0x00000000,
383 (0x0400 << 16) | (0xc778 >> 2),
384 0x00000000,
385 (0x0400 << 16) | (0xc77c >> 2),
386 0x00000000,
387 (0x0400 << 16) | (0xc780 >> 2),
388 0x00000000,
389 (0x0400 << 16) | (0xc784 >> 2),
390 0x00000000,
391 (0x0400 << 16) | (0xc788 >> 2),
392 0x00000000,
393 (0x0400 << 16) | (0xc78c >> 2),
394 0x00000000,
395 (0x0400 << 16) | (0xc798 >> 2),
396 0x00000000,
397 (0x0400 << 16) | (0xc79c >> 2),
398 0x00000000,
399 (0x0400 << 16) | (0xc7a0 >> 2),
400 0x00000000,
401 (0x0400 << 16) | (0xc7a4 >> 2),
402 0x00000000,
403 (0x0400 << 16) | (0xc7a8 >> 2),
404 0x00000000,
405 (0x0400 << 16) | (0xc7ac >> 2),
406 0x00000000,
407 (0x0400 << 16) | (0xc7b0 >> 2),
408 0x00000000,
409 (0x0400 << 16) | (0xc7b4 >> 2),
410 0x00000000,
411 (0x0e00 << 16) | (0x9100 >> 2),
412 0x00000000,
413 (0x0e00 << 16) | (0x3c010 >> 2),
414 0x00000000,
415 (0x0e00 << 16) | (0x92a8 >> 2),
416 0x00000000,
417 (0x0e00 << 16) | (0x92ac >> 2),
418 0x00000000,
419 (0x0e00 << 16) | (0x92b4 >> 2),
420 0x00000000,
421 (0x0e00 << 16) | (0x92b8 >> 2),
422 0x00000000,
423 (0x0e00 << 16) | (0x92bc >> 2),
424 0x00000000,
425 (0x0e00 << 16) | (0x92c0 >> 2),
426 0x00000000,
427 (0x0e00 << 16) | (0x92c4 >> 2),
428 0x00000000,
429 (0x0e00 << 16) | (0x92c8 >> 2),
430 0x00000000,
431 (0x0e00 << 16) | (0x92cc >> 2),
432 0x00000000,
433 (0x0e00 << 16) | (0x92d0 >> 2),
434 0x00000000,
435 (0x0e00 << 16) | (0x8c00 >> 2),
436 0x00000000,
437 (0x0e00 << 16) | (0x8c04 >> 2),
438 0x00000000,
439 (0x0e00 << 16) | (0x8c20 >> 2),
440 0x00000000,
441 (0x0e00 << 16) | (0x8c38 >> 2),
442 0x00000000,
443 (0x0e00 << 16) | (0x8c3c >> 2),
444 0x00000000,
445 (0x0e00 << 16) | (0xae00 >> 2),
446 0x00000000,
447 (0x0e00 << 16) | (0x9604 >> 2),
448 0x00000000,
449 (0x0e00 << 16) | (0xac08 >> 2),
450 0x00000000,
451 (0x0e00 << 16) | (0xac0c >> 2),
452 0x00000000,
453 (0x0e00 << 16) | (0xac10 >> 2),
454 0x00000000,
455 (0x0e00 << 16) | (0xac14 >> 2),
456 0x00000000,
457 (0x0e00 << 16) | (0xac58 >> 2),
458 0x00000000,
459 (0x0e00 << 16) | (0xac68 >> 2),
460 0x00000000,
461 (0x0e00 << 16) | (0xac6c >> 2),
462 0x00000000,
463 (0x0e00 << 16) | (0xac70 >> 2),
464 0x00000000,
465 (0x0e00 << 16) | (0xac74 >> 2),
466 0x00000000,
467 (0x0e00 << 16) | (0xac78 >> 2),
468 0x00000000,
469 (0x0e00 << 16) | (0xac7c >> 2),
470 0x00000000,
471 (0x0e00 << 16) | (0xac80 >> 2),
472 0x00000000,
473 (0x0e00 << 16) | (0xac84 >> 2),
474 0x00000000,
475 (0x0e00 << 16) | (0xac88 >> 2),
476 0x00000000,
477 (0x0e00 << 16) | (0xac8c >> 2),
478 0x00000000,
479 (0x0e00 << 16) | (0x970c >> 2),
480 0x00000000,
481 (0x0e00 << 16) | (0x9714 >> 2),
482 0x00000000,
483 (0x0e00 << 16) | (0x9718 >> 2),
484 0x00000000,
485 (0x0e00 << 16) | (0x971c >> 2),
486 0x00000000,
487 (0x0e00 << 16) | (0x31068 >> 2),
488 0x00000000,
489 (0x4e00 << 16) | (0x31068 >> 2),
490 0x00000000,
491 (0x5e00 << 16) | (0x31068 >> 2),
492 0x00000000,
493 (0x6e00 << 16) | (0x31068 >> 2),
494 0x00000000,
495 (0x7e00 << 16) | (0x31068 >> 2),
496 0x00000000,
497 (0x8e00 << 16) | (0x31068 >> 2),
498 0x00000000,
499 (0x9e00 << 16) | (0x31068 >> 2),
500 0x00000000,
501 (0xae00 << 16) | (0x31068 >> 2),
502 0x00000000,
503 (0xbe00 << 16) | (0x31068 >> 2),
504 0x00000000,
505 (0x0e00 << 16) | (0xcd10 >> 2),
506 0x00000000,
507 (0x0e00 << 16) | (0xcd14 >> 2),
508 0x00000000,
509 (0x0e00 << 16) | (0x88b0 >> 2),
510 0x00000000,
511 (0x0e00 << 16) | (0x88b4 >> 2),
512 0x00000000,
513 (0x0e00 << 16) | (0x88b8 >> 2),
514 0x00000000,
515 (0x0e00 << 16) | (0x88bc >> 2),
516 0x00000000,
517 (0x0400 << 16) | (0x89c0 >> 2),
518 0x00000000,
519 (0x0e00 << 16) | (0x88c4 >> 2),
520 0x00000000,
521 (0x0e00 << 16) | (0x88c8 >> 2),
522 0x00000000,
523 (0x0e00 << 16) | (0x88d0 >> 2),
524 0x00000000,
525 (0x0e00 << 16) | (0x88d4 >> 2),
526 0x00000000,
527 (0x0e00 << 16) | (0x88d8 >> 2),
528 0x00000000,
529 (0x0e00 << 16) | (0x8980 >> 2),
530 0x00000000,
531 (0x0e00 << 16) | (0x30938 >> 2),
532 0x00000000,
533 (0x0e00 << 16) | (0x3093c >> 2),
534 0x00000000,
535 (0x0e00 << 16) | (0x30940 >> 2),
536 0x00000000,
537 (0x0e00 << 16) | (0x89a0 >> 2),
538 0x00000000,
539 (0x0e00 << 16) | (0x30900 >> 2),
540 0x00000000,
541 (0x0e00 << 16) | (0x30904 >> 2),
542 0x00000000,
543 (0x0e00 << 16) | (0x89b4 >> 2),
544 0x00000000,
545 (0x0e00 << 16) | (0x3c210 >> 2),
546 0x00000000,
547 (0x0e00 << 16) | (0x3c214 >> 2),
548 0x00000000,
549 (0x0e00 << 16) | (0x3c218 >> 2),
550 0x00000000,
551 (0x0e00 << 16) | (0x8904 >> 2),
552 0x00000000,
553 0x5,
554 (0x0e00 << 16) | (0x8c28 >> 2),
555 (0x0e00 << 16) | (0x8c2c >> 2),
556 (0x0e00 << 16) | (0x8c30 >> 2),
557 (0x0e00 << 16) | (0x8c34 >> 2),
558 (0x0e00 << 16) | (0x9600 >> 2),
562 (0x0e00 << 16) | (0xc12c >> 2),
563 0x00000000,
564 (0x0e00 << 16) | (0xc140 >> 2),
565 0x00000000,
566 (0x0e00 << 16) | (0xc150 >> 2),
567 0x00000000,
568 (0x0e00 << 16) | (0xc15c >> 2),
569 0x00000000,
570 (0x0e00 << 16) | (0xc168 >> 2),
571 0x00000000,
572 (0x0e00 << 16) | (0xc170 >> 2),
573 0x00000000,
574 (0x0e00 << 16) | (0xc204 >> 2),
575 0x00000000,
576 (0x0e00 << 16) | (0xc2b4 >> 2),
577 0x00000000,
578 (0x0e00 << 16) | (0xc2b8 >> 2),
579 0x00000000,
580 (0x0e00 << 16) | (0xc2bc >> 2),
581 0x00000000,
582 (0x0e00 << 16) | (0xc2c0 >> 2),
583 0x00000000,
584 (0x0e00 << 16) | (0x8228 >> 2),
585 0x00000000,
586 (0x0e00 << 16) | (0x829c >> 2),
587 0x00000000,
588 (0x0e00 << 16) | (0x869c >> 2),
589 0x00000000,
590 (0x0600 << 16) | (0x98f4 >> 2),
591 0x00000000,
592 (0x0e00 << 16) | (0x98f8 >> 2),
593 0x00000000,
594 (0x0e00 << 16) | (0x9900 >> 2),
595 0x00000000,
596 (0x0e00 << 16) | (0xc260 >> 2),
597 0x00000000,
598 (0x0e00 << 16) | (0x90e8 >> 2),
599 0x00000000,
600 (0x0e00 << 16) | (0x3c000 >> 2),
601 0x00000000,
602 (0x0e00 << 16) | (0x3c00c >> 2),
603 0x00000000,
604 (0x0e00 << 16) | (0x8c1c >> 2),
605 0x00000000,
606 (0x0e00 << 16) | (0x9700 >> 2),
607 0x00000000,
608 (0x0e00 << 16) | (0xcd20 >> 2),
609 0x00000000,
610 (0x4e00 << 16) | (0xcd20 >> 2),
611 0x00000000,
612 (0x5e00 << 16) | (0xcd20 >> 2),
613 0x00000000,
614 (0x6e00 << 16) | (0xcd20 >> 2),
615 0x00000000,
616 (0x7e00 << 16) | (0xcd20 >> 2),
617 0x00000000,
618 (0x0e00 << 16) | (0x89bc >> 2),
619 0x00000000,
620 (0x0e00 << 16) | (0x8900 >> 2),
621 0x00000000,
622 0x3,
623 (0x0e00 << 16) | (0xc130 >> 2),
624 0x00000000,
625 (0x0e00 << 16) | (0xc134 >> 2),
626 0x00000000,
627 (0x0e00 << 16) | (0xc1fc >> 2),
628 0x00000000,
629 (0x0e00 << 16) | (0xc208 >> 2),
630 0x00000000,
631 (0x0e00 << 16) | (0xc264 >> 2),
632 0x00000000,
633 (0x0e00 << 16) | (0xc268 >> 2),
634 0x00000000,
635 (0x0e00 << 16) | (0xc26c >> 2),
636 0x00000000,
637 (0x0e00 << 16) | (0xc270 >> 2),
638 0x00000000,
639 (0x0e00 << 16) | (0xc274 >> 2),
640 0x00000000,
641 (0x0e00 << 16) | (0xc28c >> 2),
642 0x00000000,
643 (0x0e00 << 16) | (0xc290 >> 2),
644 0x00000000,
645 (0x0e00 << 16) | (0xc294 >> 2),
646 0x00000000,
647 (0x0e00 << 16) | (0xc298 >> 2),
648 0x00000000,
649 (0x0e00 << 16) | (0xc2a0 >> 2),
650 0x00000000,
651 (0x0e00 << 16) | (0xc2a4 >> 2),
652 0x00000000,
653 (0x0e00 << 16) | (0xc2a8 >> 2),
654 0x00000000,
655 (0x0e00 << 16) | (0xc2ac >> 2),
656 0x00000000,
657 (0x0e00 << 16) | (0x301d0 >> 2),
658 0x00000000,
659 (0x0e00 << 16) | (0x30238 >> 2),
660 0x00000000,
661 (0x0e00 << 16) | (0x30250 >> 2),
662 0x00000000,
663 (0x0e00 << 16) | (0x30254 >> 2),
664 0x00000000,
665 (0x0e00 << 16) | (0x30258 >> 2),
666 0x00000000,
667 (0x0e00 << 16) | (0x3025c >> 2),
668 0x00000000,
669 (0x4e00 << 16) | (0xc900 >> 2),
670 0x00000000,
671 (0x5e00 << 16) | (0xc900 >> 2),
672 0x00000000,
673 (0x6e00 << 16) | (0xc900 >> 2),
674 0x00000000,
675 (0x7e00 << 16) | (0xc900 >> 2),
676 0x00000000,
677 (0x4e00 << 16) | (0xc904 >> 2),
678 0x00000000,
679 (0x5e00 << 16) | (0xc904 >> 2),
680 0x00000000,
681 (0x6e00 << 16) | (0xc904 >> 2),
682 0x00000000,
683 (0x7e00 << 16) | (0xc904 >> 2),
684 0x00000000,
685 (0x4e00 << 16) | (0xc908 >> 2),
686 0x00000000,
687 (0x5e00 << 16) | (0xc908 >> 2),
688 0x00000000,
689 (0x6e00 << 16) | (0xc908 >> 2),
690 0x00000000,
691 (0x7e00 << 16) | (0xc908 >> 2),
692 0x00000000,
693 (0x4e00 << 16) | (0xc90c >> 2),
694 0x00000000,
695 (0x5e00 << 16) | (0xc90c >> 2),
696 0x00000000,
697 (0x6e00 << 16) | (0xc90c >> 2),
698 0x00000000,
699 (0x7e00 << 16) | (0xc90c >> 2),
700 0x00000000,
701 (0x4e00 << 16) | (0xc910 >> 2),
702 0x00000000,
703 (0x5e00 << 16) | (0xc910 >> 2),
704 0x00000000,
705 (0x6e00 << 16) | (0xc910 >> 2),
706 0x00000000,
707 (0x7e00 << 16) | (0xc910 >> 2),
708 0x00000000,
709 (0x0e00 << 16) | (0xc99c >> 2),
710 0x00000000,
711 (0x0e00 << 16) | (0x9834 >> 2),
712 0x00000000,
713 (0x0000 << 16) | (0x30f00 >> 2),
714 0x00000000,
715 (0x0000 << 16) | (0x30f04 >> 2),
716 0x00000000,
717 (0x0000 << 16) | (0x30f08 >> 2),
718 0x00000000,
719 (0x0000 << 16) | (0x30f0c >> 2),
720 0x00000000,
721 (0x0600 << 16) | (0x9b7c >> 2),
722 0x00000000,
723 (0x0e00 << 16) | (0x8a14 >> 2),
724 0x00000000,
725 (0x0e00 << 16) | (0x8a18 >> 2),
726 0x00000000,
727 (0x0600 << 16) | (0x30a00 >> 2),
728 0x00000000,
729 (0x0e00 << 16) | (0x8bf0 >> 2),
730 0x00000000,
731 (0x0e00 << 16) | (0x8bcc >> 2),
732 0x00000000,
733 (0x0e00 << 16) | (0x8b24 >> 2),
734 0x00000000,
735 (0x0e00 << 16) | (0x30a04 >> 2),
736 0x00000000,
737 (0x0600 << 16) | (0x30a10 >> 2),
738 0x00000000,
739 (0x0600 << 16) | (0x30a14 >> 2),
740 0x00000000,
741 (0x0600 << 16) | (0x30a18 >> 2),
742 0x00000000,
743 (0x0600 << 16) | (0x30a2c >> 2),
744 0x00000000,
745 (0x0e00 << 16) | (0xc700 >> 2),
746 0x00000000,
747 (0x0e00 << 16) | (0xc704 >> 2),
748 0x00000000,
749 (0x0e00 << 16) | (0xc708 >> 2),
750 0x00000000,
751 (0x0e00 << 16) | (0xc768 >> 2),
752 0x00000000,
753 (0x0400 << 16) | (0xc770 >> 2),
754 0x00000000,
755 (0x0400 << 16) | (0xc774 >> 2),
756 0x00000000,
757 (0x0400 << 16) | (0xc798 >> 2),
758 0x00000000,
759 (0x0400 << 16) | (0xc79c >> 2),
760 0x00000000,
761 (0x0e00 << 16) | (0x9100 >> 2),
762 0x00000000,
763 (0x0e00 << 16) | (0x3c010 >> 2),
764 0x00000000,
765 (0x0e00 << 16) | (0x8c00 >> 2),
766 0x00000000,
767 (0x0e00 << 16) | (0x8c04 >> 2),
768 0x00000000,
769 (0x0e00 << 16) | (0x8c20 >> 2),
770 0x00000000,
771 (0x0e00 << 16) | (0x8c38 >> 2),
772 0x00000000,
773 (0x0e00 << 16) | (0x8c3c >> 2),
774 0x00000000,
775 (0x0e00 << 16) | (0xae00 >> 2),
776 0x00000000,
777 (0x0e00 << 16) | (0x9604 >> 2),
778 0x00000000,
779 (0x0e00 << 16) | (0xac08 >> 2),
780 0x00000000,
781 (0x0e00 << 16) | (0xac0c >> 2),
782 0x00000000,
783 (0x0e00 << 16) | (0xac10 >> 2),
784 0x00000000,
785 (0x0e00 << 16) | (0xac14 >> 2),
786 0x00000000,
787 (0x0e00 << 16) | (0xac58 >> 2),
788 0x00000000,
789 (0x0e00 << 16) | (0xac68 >> 2),
790 0x00000000,
791 (0x0e00 << 16) | (0xac6c >> 2),
792 0x00000000,
793 (0x0e00 << 16) | (0xac70 >> 2),
794 0x00000000,
795 (0x0e00 << 16) | (0xac74 >> 2),
796 0x00000000,
797 (0x0e00 << 16) | (0xac78 >> 2),
798 0x00000000,
799 (0x0e00 << 16) | (0xac7c >> 2),
800 0x00000000,
801 (0x0e00 << 16) | (0xac80 >> 2),
802 0x00000000,
803 (0x0e00 << 16) | (0xac84 >> 2),
804 0x00000000,
805 (0x0e00 << 16) | (0xac88 >> 2),
806 0x00000000,
807 (0x0e00 << 16) | (0xac8c >> 2),
808 0x00000000,
809 (0x0e00 << 16) | (0x970c >> 2),
810 0x00000000,
811 (0x0e00 << 16) | (0x9714 >> 2),
812 0x00000000,
813 (0x0e00 << 16) | (0x9718 >> 2),
814 0x00000000,
815 (0x0e00 << 16) | (0x971c >> 2),
816 0x00000000,
817 (0x0e00 << 16) | (0x31068 >> 2),
818 0x00000000,
819 (0x4e00 << 16) | (0x31068 >> 2),
820 0x00000000,
821 (0x5e00 << 16) | (0x31068 >> 2),
822 0x00000000,
823 (0x6e00 << 16) | (0x31068 >> 2),
824 0x00000000,
825 (0x7e00 << 16) | (0x31068 >> 2),
826 0x00000000,
827 (0x0e00 << 16) | (0xcd10 >> 2),
828 0x00000000,
829 (0x0e00 << 16) | (0xcd14 >> 2),
830 0x00000000,
831 (0x0e00 << 16) | (0x88b0 >> 2),
832 0x00000000,
833 (0x0e00 << 16) | (0x88b4 >> 2),
834 0x00000000,
835 (0x0e00 << 16) | (0x88b8 >> 2),
836 0x00000000,
837 (0x0e00 << 16) | (0x88bc >> 2),
838 0x00000000,
839 (0x0400 << 16) | (0x89c0 >> 2),
840 0x00000000,
841 (0x0e00 << 16) | (0x88c4 >> 2),
842 0x00000000,
843 (0x0e00 << 16) | (0x88c8 >> 2),
844 0x00000000,
845 (0x0e00 << 16) | (0x88d0 >> 2),
846 0x00000000,
847 (0x0e00 << 16) | (0x88d4 >> 2),
848 0x00000000,
849 (0x0e00 << 16) | (0x88d8 >> 2),
850 0x00000000,
851 (0x0e00 << 16) | (0x8980 >> 2),
852 0x00000000,
853 (0x0e00 << 16) | (0x30938 >> 2),
854 0x00000000,
855 (0x0e00 << 16) | (0x3093c >> 2),
856 0x00000000,
857 (0x0e00 << 16) | (0x30940 >> 2),
858 0x00000000,
859 (0x0e00 << 16) | (0x89a0 >> 2),
860 0x00000000,
861 (0x0e00 << 16) | (0x30900 >> 2),
862 0x00000000,
863 (0x0e00 << 16) | (0x30904 >> 2),
864 0x00000000,
865 (0x0e00 << 16) | (0x89b4 >> 2),
866 0x00000000,
867 (0x0e00 << 16) | (0x3e1fc >> 2),
868 0x00000000,
869 (0x0e00 << 16) | (0x3c210 >> 2),
870 0x00000000,
871 (0x0e00 << 16) | (0x3c214 >> 2),
872 0x00000000,
873 (0x0e00 << 16) | (0x3c218 >> 2),
874 0x00000000,
875 (0x0e00 << 16) | (0x8904 >> 2),
876 0x00000000,
877 0x5,
878 (0x0e00 << 16) | (0x8c28 >> 2),
879 (0x0e00 << 16) | (0x8c2c >> 2),
880 (0x0e00 << 16) | (0x8c30 >> 2),
881 (0x0e00 << 16) | (0x8c34 >> 2),
882 (0x0e00 << 16) | (0x9600 >> 2),
910 * Returns 0 on success, error on failure.
1018 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1019 tile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1020 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1021 macrotile[reg_offset] = 0; in gfx_v7_0_tiling_mode_table_init()
1025 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1128 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1185 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1187 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1192 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1311 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1368 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1370 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1378 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1481 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in gfx_v7_0_tiling_mode_table_init()
1538 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1540 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v7_0_tiling_mode_table_init()
1554 * 0xffffffff means broadcast to all SEs or SHs (CIK).
1564 if (instance == 0xffffffff) in gfx_v7_0_select_se_sh()
1565 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v7_0_select_se_sh()
1567 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v7_0_select_se_sh()
1569 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1572 else if (se_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1575 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1615 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1627 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1631 *rconf |= 0x0; in gfx_v7_0_raster_config()
1632 *rconf1 |= 0x0; in gfx_v7_0_raster_config()
1635 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); in gfx_v7_0_raster_config()
1652 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1653 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1661 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v7_0_write_harvested_raster_configs()
1665 if (!se_mask[0] && !se_mask[1]) { in gfx_v7_0_write_harvested_raster_configs()
1674 for (se = 0; se < num_se; se++) { in gfx_v7_0_write_harvested_raster_configs()
1740 gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_write_harvested_raster_configs()
1746 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_write_harvested_raster_configs()
1760 u32 raster_config = 0, raster_config_1 = 0; in gfx_v7_0_setup_rb()
1761 u32 active_rbs = 0; in gfx_v7_0_setup_rb()
1767 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1768 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1769 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1775 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1796 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_setup_rb()
1797 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1798 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1809 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_setup_rb()
1813 #define DEFAULT_SH_MEM_BASES (0x6000)
1830 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v7_0_init_compute_vmid()
1831 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v7_0_init_compute_vmid()
1832 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v7_0_init_compute_vmid()
1840 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_init_compute_vmid()
1844 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v7_0_init_compute_vmid()
1847 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_init_compute_vmid()
1853 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); in gfx_v7_0_init_compute_vmid()
1854 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); in gfx_v7_0_init_compute_vmid()
1855 WREG32(amdgpu_gds_reg_offset[i].gws, 0); in gfx_v7_0_init_compute_vmid()
1856 WREG32(amdgpu_gds_reg_offset[i].oa, 0); in gfx_v7_0_init_compute_vmid()
1871 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0); in gfx_v7_0_init_gds_vmid()
1872 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0); in gfx_v7_0_init_gds_vmid()
1873 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0); in gfx_v7_0_init_gds_vmid()
1874 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0); in gfx_v7_0_init_gds_vmid()
1897 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); in gfx_v7_0_constants_init()
1911 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | in gfx_v7_0_constants_init()
1912 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); in gfx_v7_0_constants_init()
1919 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_constants_init()
1923 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, in gfx_v7_0_constants_init()
1929 sh_mem_cfg = REG_SET_FIELD(sh_mem_cfg, SH_MEM_CONFIG, PRIVATE_ATC, 0); in gfx_v7_0_constants_init()
1931 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG, in gfx_v7_0_constants_init()
1940 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { in gfx_v7_0_constants_init()
1941 if (i == 0) in gfx_v7_0_constants_init()
1942 sh_mem_base = 0; in gfx_v7_0_constants_init()
1945 cik_srbm_select(adev, 0, 0, 0, i); in gfx_v7_0_constants_init()
1949 WREG32(mmSH_MEM_APE1_LIMIT, 0); in gfx_v7_0_constants_init()
1952 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_constants_init()
1958 WREG32(mmSX_DEBUG_1, 0x20); in gfx_v7_0_constants_init()
1960 WREG32(mmTA_CNTL_AUX, 0x00010000); in gfx_v7_0_constants_init()
1963 tmp |= 0x03000000; in gfx_v7_0_constants_init()
1968 WREG32(mmDB_DEBUG, 0); in gfx_v7_0_constants_init()
1970 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
1971 tmp |= 0x00000400; in gfx_v7_0_constants_init()
1974 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
1975 tmp |= 0x00020200; in gfx_v7_0_constants_init()
1978 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
1979 tmp |= 0x00018208; in gfx_v7_0_constants_init()
1992 WREG32(mmCP_PERFMON_CNTL, 0); in gfx_v7_0_constants_init()
1994 WREG32(mmSQ_CONFIG, 0); in gfx_v7_0_constants_init()
2005 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); in gfx_v7_0_constants_init()
2031 * Returns 0 on success, error on failure.
2036 uint32_t tmp = 0; in gfx_v7_0_ring_test_ring()
2040 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ring()
2047 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v7_0_ring_test_ring()
2050 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_ring_test_ring()
2052 if (tmp == 0xDEADBEEF) in gfx_v7_0_ring_test_ring()
2071 int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; in gfx_v7_0_ring_emit_hdp_flush()
2096 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_hdp_flush()
2101 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2105 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v7_0_ring_emit_vgt_flush()
2107 EVENT_INDEX(0)); in gfx_v7_0_ring_emit_vgt_flush()
2136 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2137 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2138 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()
2148 (exec ? EOP_EXEC : 0))); in gfx_v7_0_ring_emit_fence_gfx()
2149 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_gfx()
2150 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in gfx_v7_0_ring_emit_fence_gfx()
2151 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()
2180 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
2181 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_fence_compute()
2210 u32 header, control = 0; in gfx_v7_0_ring_emit_ib_gfx()
2214 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2215 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_ib_gfx()
2228 (2 << 0) | in gfx_v7_0_ring_emit_ib_gfx()
2230 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v7_0_ring_emit_ib_gfx()
2231 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_gfx()
2251 * GDS to 0 for this ring (me/pipe). in gfx_v7_0_ring_emit_ib_compute()
2262 (2 << 0) | in gfx_v7_0_ring_emit_ib_compute()
2264 (ib->gpu_addr & 0xFFFFFFFC)); in gfx_v7_0_ring_emit_ib_compute()
2265 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in gfx_v7_0_ring_emit_ib_compute()
2271 uint32_t dw2 = 0; in gfx_v7_ring_emit_cntxcntl()
2273 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v7_ring_emit_cntxcntl()
2277 dw2 |= 0x8001; in gfx_v7_ring_emit_cntxcntl()
2279 dw2 |= 0x01000000; in gfx_v7_ring_emit_cntxcntl()
2281 dw2 |= 0x10002; in gfx_v7_ring_emit_cntxcntl()
2286 amdgpu_ring_write(ring, 0); in gfx_v7_ring_emit_cntxcntl()
2297 * Returns 0 on success, error on failure.
2304 uint32_t tmp = 0; in gfx_v7_0_ring_test_ib()
2307 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ib()
2308 memset(&ib, 0, sizeof(ib)); in gfx_v7_0_ring_test_ib()
2313 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib()
2315 ib.ptr[2] = 0xDEADBEEF; in gfx_v7_0_ring_test_ib()
2323 if (r == 0) { in gfx_v7_0_ring_test_ib()
2326 } else if (r < 0) { in gfx_v7_0_ring_test_ib()
2330 if (tmp == 0xDEADBEEF) in gfx_v7_0_ring_test_ib()
2331 r = 0; in gfx_v7_0_ring_test_ib()
2375 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2389 * Returns 0 for success, -EINVAL if the ucode is not available.
2423 WREG32(mmCP_PFP_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2424 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2433 WREG32(mmCP_CE_UCODE_ADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2434 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2443 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2444 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_gfx_load_microcode()
2448 return 0; in gfx_v7_0_cp_gfx_load_microcode()
2458 * Returns 0 for success, error for failure.
2462 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_start()
2469 WREG32(mmCP_ENDIAN_SWAP, 0); in gfx_v7_0_cp_gfx_start()
2483 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2484 amdgpu_ring_write(ring, 0x8000); in gfx_v7_0_cp_gfx_start()
2487 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2491 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2492 amdgpu_ring_write(ring, 0x80000000); in gfx_v7_0_cp_gfx_start()
2500 for (i = 0; i < ext->reg_count; i++) in gfx_v7_0_cp_gfx_start()
2508 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_cp_gfx_start()
2509 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_cp_gfx_start()
2511 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v7_0_cp_gfx_start()
2514 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
2515 amdgpu_ring_write(ring, 0); in gfx_v7_0_cp_gfx_start()
2518 amdgpu_ring_write(ring, 0x00000316); in gfx_v7_0_cp_gfx_start()
2519 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in gfx_v7_0_cp_gfx_start()
2520 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in gfx_v7_0_cp_gfx_start()
2524 return 0; in gfx_v7_0_cp_gfx_start()
2534 * Returns 0 for success, error for failure.
2544 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); in gfx_v7_0_cp_gfx_resume()
2546 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in gfx_v7_0_cp_gfx_resume()
2549 WREG32(mmCP_RB_WPTR_DELAY, 0); in gfx_v7_0_cp_gfx_resume()
2551 /* set the RB to use vmid 0 */ in gfx_v7_0_cp_gfx_resume()
2552 WREG32(mmCP_RB_VMID, 0); in gfx_v7_0_cp_gfx_resume()
2554 WREG32(mmSCRATCH_ADDR, 0); in gfx_v7_0_cp_gfx_resume()
2556 /* ring 0 - compute and gfx */ in gfx_v7_0_cp_gfx_resume()
2558 ring = &adev->gfx.gfx_ring[0]; in gfx_v7_0_cp_gfx_resume()
2568 ring->wptr = 0; in gfx_v7_0_cp_gfx_resume()
2574 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v7_0_cp_gfx_resume()
2577 WREG32(mmSCRATCH_UMSK, 0); in gfx_v7_0_cp_gfx_resume()
2592 return 0; in gfx_v7_0_cp_gfx_resume()
2641 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
2654 * Returns 0 for success, -EINVAL if the ucode is not available.
2678 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2679 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_compute_load_microcode()
2681 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2700 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2701 for (i = 0; i < fw_size; i++) in gfx_v7_0_cp_compute_load_microcode()
2703 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0); in gfx_v7_0_cp_compute_load_microcode()
2706 return 0; in gfx_v7_0_cp_compute_load_microcode()
2721 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()
2739 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v7_0_mec_init()
2761 memset(hpd, 0, mec_hpd_size); in gfx_v7_0_mec_init()
2766 return 0; in gfx_v7_0_mec_init()
2780 cik_srbm_select(adev, mec + 1, pipe, 0, 0); in gfx_v7_0_compute_pipe_init()
2787 WREG32(mmCP_HPD_EOP_VMID, 0); in gfx_v7_0_compute_pipe_init()
2795 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_pipe_init()
2806 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_mqd_deactivate()
2815 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0); in gfx_v7_0_mqd_deactivate()
2816 WREG32(mmCP_HQD_PQ_RPTR, 0); in gfx_v7_0_mqd_deactivate()
2817 WREG32(mmCP_HQD_PQ_WPTR, 0); in gfx_v7_0_mqd_deactivate()
2820 return 0; in gfx_v7_0_mqd_deactivate()
2832 memset(mqd, 0, sizeof(struct cik_mqd)); in gfx_v7_0_mqd_init()
2834 mqd->header = 0xC0310800; in gfx_v7_0_mqd_init()
2835 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v7_0_mqd_init()
2836 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v7_0_mqd_init()
2837 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v7_0_mqd_init()
2838 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v7_0_mqd_init()
2849 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2852 /* set MQD vmid to 0 */ in gfx_v7_0_mqd_init()
2885 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2886 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
2890 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v7_0_mqd_init()
2892 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
2910 mqd->cp_hqd_pq_doorbell_control = 0; in gfx_v7_0_mqd_init()
2914 ring->wptr = 0; in gfx_v7_0_mqd_init()
2919 mqd->cp_hqd_vmid = 0; in gfx_v7_0_mqd_init()
2954 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v7_0_mqd_commit()
2965 return 0; in gfx_v7_0_mqd_commit()
2984 cik_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v7_0_compute_queue_init()
2990 cik_srbm_select(adev, 0, 0, 0, 0); in gfx_v7_0_compute_queue_init()
2995 return 0; in gfx_v7_0_compute_queue_init()
3005 * Returns 0 for success, error for failure.
3019 for (i = 0; i < adev->gfx.mec.num_mec; i++) in gfx_v7_0_cp_compute_resume()
3020 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) in gfx_v7_0_cp_compute_resume()
3024 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3034 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()
3039 return 0; in gfx_v7_0_cp_compute_resume()
3059 return 0; in gfx_v7_0_cp_load_microcode()
3095 return 0; in gfx_v7_0_cp_resume()
3116 amdgpu_ring_write(ring, addr & 0xfffffffc); in gfx_v7_0_ring_emit_pipeline_sync()
3117 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in gfx_v7_0_ring_emit_pipeline_sync()
3119 amdgpu_ring_write(ring, 0xffffffff); in gfx_v7_0_ring_emit_pipeline_sync()
3124 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_pipeline_sync()
3125 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_pipeline_sync()
3126 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_pipeline_sync()
3127 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_pipeline_sync()
3133 * VMID 0 is the physical GPU addresses as used by the kernel.
3156 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in gfx_v7_0_ring_emit_vm_flush()
3157 WAIT_REG_MEM_FUNCTION(0) | /* always */ in gfx_v7_0_ring_emit_vm_flush()
3158 WAIT_REG_MEM_ENGINE(0))); /* me */ in gfx_v7_0_ring_emit_vm_flush()
3160 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3161 amdgpu_ring_write(ring, 0); /* ref */ in gfx_v7_0_ring_emit_vm_flush()
3162 amdgpu_ring_write(ring, 0); /* mask */ in gfx_v7_0_ring_emit_vm_flush()
3163 amdgpu_ring_write(ring, 0x20); /* poll interval */ in gfx_v7_0_ring_emit_vm_flush()
3168 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v7_0_ring_emit_vm_flush()
3169 amdgpu_ring_write(ring, 0x0); in gfx_v7_0_ring_emit_vm_flush()
3172 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3173 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3174 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_vm_flush()
3175 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_vm_flush()
3186 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()
3188 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_wreg()
3246 /* init spm vmid with 0xf */ in gfx_v7_0_rlc_init()
3248 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v7_0_rlc_init()
3250 return 0; in gfx_v7_0_rlc_init()
3271 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_wait_for_rlc_serdes()
3272 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
3273 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_wait_for_rlc_serdes()
3274 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3275 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3281 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_wait_for_rlc_serdes()
3288 for (k = 0; k < adev->usec_timeout; k++) { in gfx_v7_0_wait_for_rlc_serdes()
3289 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3316 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_halt_rlc()
3317 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3337 tmp = 0x1 | (1 << 1); in gfx_v7_0_set_safe_mode()
3342 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_set_safe_mode()
3348 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_set_safe_mode()
3349 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_set_safe_mode()
3359 tmp = 0x1 | (0 << 1); in gfx_v7_0_unset_safe_mode()
3372 WREG32(mmRLC_CNTL, 0); in gfx_v7_0_rlc_stop()
3414 * Returns 0 for success, -EINVAL if the ucode is not available.
3435 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3442 WREG32(mmRLC_LB_CNTR_INIT, 0); in gfx_v7_0_rlc_resume()
3443 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); in gfx_v7_0_rlc_resume()
3446 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_rlc_resume()
3447 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); in gfx_v7_0_rlc_resume()
3448 WREG32(mmRLC_LB_PARAMS, 0x00600408); in gfx_v7_0_rlc_resume()
3449 WREG32(mmRLC_LB_CNTL, 0x80000004); in gfx_v7_0_rlc_resume()
3452 WREG32(mmRLC_MC_CNTL, 0); in gfx_v7_0_rlc_resume()
3453 WREG32(mmRLC_UCODE_CNTL, 0); in gfx_v7_0_rlc_resume()
3458 WREG32(mmRLC_GPM_UCODE_ADDR, 0); in gfx_v7_0_rlc_resume()
3459 for (i = 0; i < fw_size; i++) in gfx_v7_0_rlc_resume()
3467 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0); in gfx_v7_0_rlc_resume()
3471 return 0; in gfx_v7_0_rlc_resume()
3502 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_cgcg()
3503 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
3504 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_cgcg()
3535 u32 data, orig, tmp = 0; in gfx_v7_0_enable_mgcg()
3548 data |= 0x00000001; in gfx_v7_0_enable_mgcg()
3549 data &= 0xfffffffd; in gfx_v7_0_enable_mgcg()
3556 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_mgcg()
3557 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3558 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3569 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT); in gfx_v7_0_enable_mgcg()
3577 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT); in gfx_v7_0_enable_mgcg()
3583 data |= 0x00000003; in gfx_v7_0_enable_mgcg()
3607 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_enable_mgcg()
3608 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3609 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in gfx_v7_0_enable_mgcg()
3667 data &= ~0x8000; in gfx_v7_0_enable_cp_pg()
3669 data |= 0x8000; in gfx_v7_0_enable_cp_pg()
3680 data &= ~0x2000; in gfx_v7_0_enable_gds_pg()
3682 data |= 0x2000; in gfx_v7_0_enable_gds_pg()
3794 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3795 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3809 for (i = 0; i < 3; i++) in gfx_v7_0_init_gfx_cgpg()
3810 WREG32(mmRLC_GPM_SCRATCH_DATA, 0); in gfx_v7_0_init_gfx_cgpg()
3814 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3828 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v7_0_init_gfx_cgpg()
3831 data = 0x10101010; in gfx_v7_0_init_gfx_cgpg()
3835 data &= ~0xff; in gfx_v7_0_init_gfx_cgpg()
3836 data |= 0x3; in gfx_v7_0_init_gfx_cgpg()
3841 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); in gfx_v7_0_init_gfx_cgpg()
3855 u32 count = 0; in gfx_v7_0_get_csb_size()
3860 return 0; in gfx_v7_0_get_csb_size()
3872 return 0; in gfx_v7_0_get_csb_size()
3887 u32 count = 0; in gfx_v7_0_get_csb_buffer()
3899 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); in gfx_v7_0_get_csb_buffer()
3900 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1); in gfx_v7_0_get_csb_buffer()
3969 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
3970 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3972 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
3977 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
3978 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3980 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
3985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
3986 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3988 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
3993 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v7_0_ring_emit_gds_switch()
3994 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
3996 amdgpu_ring_write(ring, 0); in gfx_v7_0_ring_emit_gds_switch()
4003 uint32_t value = 0; in gfx_v7_0_ring_soft_recovery()
4005 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v7_0_ring_soft_recovery()
4006 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v7_0_ring_soft_recovery()
4039 /* type 0 wave data */ in gfx_v7_0_read_wave_data()
4040 dst[(*no_fields)++] = 0; in gfx_v7_0_read_wave_data()
4067 adev, simd, wave, 0, in gfx_v7_0_read_wave_sgprs()
4114 return 0; in gfx_v7_0_early_init()
4122 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_late_init()
4126 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_late_init()
4130 return 0; in gfx_v7_0_late_init()
4152 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4153 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4154 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4155 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4169 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4170 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4171 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4172 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4186 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4187 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4188 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4189 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4205 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v7_0_gpu_early_init()
4206 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v7_0_gpu_early_init()
4207 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v7_0_gpu_early_init()
4208 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; in gfx_v7_0_gpu_early_init()
4234 …if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map… in gfx_v7_0_gpu_early_init()
4235 dimm00_addr_map = 0; in gfx_v7_0_gpu_early_init()
4236 …if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map… in gfx_v7_0_gpu_early_init()
4237 dimm01_addr_map = 0; in gfx_v7_0_gpu_early_init()
4238 …if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map… in gfx_v7_0_gpu_early_init()
4239 dimm10_addr_map = 0; in gfx_v7_0_gpu_early_init()
4240 …if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map… in gfx_v7_0_gpu_early_init()
4241 dimm11_addr_map = 0; in gfx_v7_0_gpu_early_init()
4265 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT); in gfx_v7_0_gpu_early_init()
4306 return 0; in gfx_v7_0_compute_ring_init()
4366 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v7_0_sw_init()
4379 ring_id = 0; in gfx_v7_0_sw_init()
4380 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v7_0_sw_init()
4381 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v7_0_sw_init()
4382 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v7_0_sw_init()
4383 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v7_0_sw_init()
4398 adev->gfx.ce_ram_size = 0x8000; in gfx_v7_0_sw_init()
4403 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v7_0_sw_init()
4405 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v7_0_sw_init()
4415 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_sw_fini()
4417 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()
4433 return 0; in gfx_v7_0_sw_fini()
4461 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v7_0_hw_fini()
4462 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v7_0_hw_fini()
4467 return 0; in gfx_v7_0_hw_fini()
4496 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v7_0_wait_for_idle()
4501 return 0; in gfx_v7_0_wait_for_idle()
4509 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in gfx_v7_0_soft_reset()
4556 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4570 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gfx_v7_0_soft_reset()
4583 return 0; in gfx_v7_0_soft_reset()
4621 case 0: in gfx_v7_0_set_compute_eop_interrupt_state()
4680 return 0; in gfx_v7_0_set_priv_reg_fault_state()
4705 return 0; in gfx_v7_0_set_priv_inst_fault_state()
4718 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4730 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state); in gfx_v7_0_set_eop_interrupt_state()
4744 return 0; in gfx_v7_0_set_eop_interrupt_state()
4756 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v7_0_eop_irq()
4757 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v7_0_eop_irq()
4759 case 0: in gfx_v7_0_eop_irq()
4760 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v7_0_eop_irq()
4764 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()
4771 return 0; in gfx_v7_0_eop_irq()
4781 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v7_0_fault()
4782 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v7_0_fault()
4784 case 0: in gfx_v7_0_fault()
4785 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); in gfx_v7_0_fault()
4789 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()
4804 return 0; in gfx_v7_0_priv_reg_irq()
4814 return 0; in gfx_v7_0_priv_inst_irq()
4837 return 0; in gfx_v7_0_set_clockgating_state()
4862 return 0; in gfx_v7_0_set_powergating_state()
4872 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v7_0_emit_mem_sync()
4873 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v7_0_emit_mem_sync()
4874 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v7_0_emit_mem_sync()
4884 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v7_0_emit_mem_sync_compute()
4885 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */ in gfx_v7_0_emit_mem_sync_compute()
4886 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v7_0_emit_mem_sync_compute()
4887 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v7_0_emit_mem_sync_compute()
4888 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ in gfx_v7_0_emit_mem_sync_compute()
4910 .align_mask = 0xff,
4911 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4944 .align_mask = 0xff,
4945 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4978 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v7_0_set_ring_funcs()
4980 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
5023 int i, j, k, counter, active_cu_number = 0; in gfx_v7_0_get_cu_info()
5024 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; in gfx_v7_0_get_cu_info()
5034 memset(cu_info, 0, sizeof(*cu_info)); in gfx_v7_0_get_cu_info()
5039 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v7_0_get_cu_info()
5040 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_get_cu_info()
5042 ao_bitmap = 0; in gfx_v7_0_get_cu_info()
5043 counter = 0; in gfx_v7_0_get_cu_info()
5044 gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v7_0_get_cu_info()
5049 cu_info->bitmap[0][i][j] = bitmap; in gfx_v7_0_get_cu_info()
5051 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v7_0_get_cu_info()
5065 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v7_0_get_cu_info()
5081 .rev = 0,
5089 .rev = 0,
5097 .rev = 0,