Lines Matching +full:0 +full:xf0ffffff
57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
60 #define regCGTT_WD_CLK_CTRL 0x5086
62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
64 #define regPC_CONFIG_CNTL_1 0x194d
103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
105 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
119 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
120 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
121 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
123 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
124 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
126 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
127 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
136 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
137 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
138 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
139 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
140 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
141 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
142 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
143 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
144 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
145 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
146 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
147 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
148 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
149 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
150 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
166 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
167 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
168 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
169 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
170 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
171 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
234 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
247 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
252 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
253 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
257 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
258 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
259 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
304 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
305 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ in gfx11_kiq_set_resources()
306 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx11_kiq_set_resources()
311 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
312 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
320 uint32_t me = 0, eng_sel = 0; in gfx11_kiq_map_queues()
325 eng_sel = 0; in gfx11_kiq_map_queues()
328 me = 0; in gfx11_kiq_map_queues()
340 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ in gfx11_kiq_map_queues()
341 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
342 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ in gfx11_kiq_map_queues()
343 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ in gfx11_kiq_map_queues()
347 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ in gfx11_kiq_map_queues()
348 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ in gfx11_kiq_map_queues()
364 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_unmap_queues()
366 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
372 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_unmap_queues()
374 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | in gfx11_kiq_unmap_queues()
385 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
386 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
387 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
396 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_query_status()
400 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | in gfx11_kiq_query_status()
401 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | in gfx11_kiq_query_status()
403 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_query_status()
434 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
442 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_init_golden_registers()
443 case IP_VERSION(11, 0, 1): in gfx_v11_0_init_golden_registers()
444 case IP_VERSION(11, 0, 4): in gfx_v11_0_init_golden_registers()
463 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
465 amdgpu_ring_write(ring, 0); in gfx_v11_0_write_data_to_reg()
476 /* memory (1) or register (0) */ in gfx_v11_0_wait_reg_mem()
483 BUG_ON(addr0 & 0x3); /* Dword align */ in gfx_v11_0_wait_reg_mem()
499 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ in gfx_v11_ring_insert_nop()
500 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); in gfx_v11_ring_insert_nop()
502 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ in gfx_v11_ring_insert_nop()
509 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
510 uint32_t tmp = 0; in gfx_v11_0_ring_test_ring()
514 WREG32(scratch, 0xCAFEDEAD); in gfx_v11_0_ring_test_ring()
523 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
528 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
532 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_test_ring()
534 if (tmp == 0xDEADBEEF) in gfx_v11_0_ring_test_ring()
560 return 0; in gfx_v11_0_ring_test_ib()
562 memset(&ib, 0, sizeof(ib)); in gfx_v11_0_ring_test_ib()
576 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
583 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
593 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
597 ib.ptr[4] = 0xDEADBEEF; in gfx_v11_0_ring_test_ib()
605 if (r == 0) { in gfx_v11_0_ring_test_ib()
608 } else if (r < 0) { in gfx_v11_0_ring_test_ib()
612 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) in gfx_v11_0_ring_test_ib()
613 r = 0; in gfx_v11_0_ring_test_ib()
639 int err = 0; in gfx_v11_0_init_toc_microcode()
652 return 0; in gfx_v11_0_init_toc_microcode()
660 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_check_fw_cp_gfx_shadow()
661 case IP_VERSION(11, 0, 0): in gfx_v11_0_check_fw_cp_gfx_shadow()
662 case IP_VERSION(11, 0, 2): in gfx_v11_0_check_fw_cp_gfx_shadow()
663 case IP_VERSION(11, 0, 3): in gfx_v11_0_check_fw_cp_gfx_shadow()
697 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
720 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && in gfx_v11_0_init_microcode()
721 adev->pdev->revision == 0xCE) in gfx_v11_0_init_microcode()
755 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
780 u32 count = 0; in gfx_v11_0_get_csb_size()
794 return 0; in gfx_v11_0_get_csb_size()
811 u32 count = 0, i; in gfx_v11_0_get_csb_buffer()
821 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
825 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
826 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
835 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_get_csb_buffer()
844 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
852 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_get_csb_buffer()
853 buffer[count++] = cpu_to_le32(0); in gfx_v11_0_get_csb_buffer()
873 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
874 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
875 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
876 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
877 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
878 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
879 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
880 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
900 /* init spm vmid with 0xf */ in gfx_v11_0_rlc_init()
902 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v11_0_rlc_init()
904 return 0; in gfx_v11_0_rlc_init()
927 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
945 memset(hpd, 0, mec_hpd_size); in gfx_v11_0_mec_init()
951 return 0; in gfx_v11_0_mec_init()
956 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
959 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
966 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
972 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
980 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
1005 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1008 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, in gfx_v11_0_read_wave_sgprs()
1042 return 0; in gfx_v11_0_get_gfx_shadow_info()
1044 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); in gfx_v11_0_get_gfx_shadow_info()
1062 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_gpu_early_init()
1063 case IP_VERSION(11, 0, 0): in gfx_v11_0_gpu_early_init()
1064 case IP_VERSION(11, 0, 2): in gfx_v11_0_gpu_early_init()
1066 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1067 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1068 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1069 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1071 case IP_VERSION(11, 0, 3): in gfx_v11_0_gpu_early_init()
1074 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1075 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1076 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1077 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1079 case IP_VERSION(11, 0, 1): in gfx_v11_0_gpu_early_init()
1080 case IP_VERSION(11, 0, 4): in gfx_v11_0_gpu_early_init()
1081 case IP_VERSION(11, 5, 0): in gfx_v11_0_gpu_early_init()
1085 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1086 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1087 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
1088 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
1095 return 0; in gfx_v11_0_gpu_early_init()
1118 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_gfx_ring_init()
1148 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_compute_ring_init()
1162 return 0; in gfx_v11_0_compute_ring_init()
1187 uint32_t total_size = 0; in gfx_v11_0_calc_toc_total_size()
1222 return 0; in gfx_v11_0_rlc_autoload_buffer_init()
1241 if (fw_size == 0) in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1250 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1263 *(uint64_t *)fw_autoload_mask |= 0x1; in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1265 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1412 adev->sdma.instance[0].fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1413 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1420 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1436 for (pipe = 0; pipe < 2; pipe++) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1437 if (pipe==0) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1470 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); in gfx_v11_0_rlc_backdoor_autoload_enable()
1482 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1483 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1485 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v11_0_rlc_backdoor_autoload_enable()
1499 return 0; in gfx_v11_0_rlc_backdoor_autoload_enable()
1545 int i, j, k, r, ring_id = 0; in gfx_v11_0_sw_init()
1546 int xcc_id = 0; in gfx_v11_0_sw_init()
1549 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1550 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1551 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1552 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1560 case IP_VERSION(11, 0, 1): in gfx_v11_0_sw_init()
1561 case IP_VERSION(11, 0, 4): in gfx_v11_0_sw_init()
1562 case IP_VERSION(11, 5, 0): in gfx_v11_0_sw_init()
1582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1583 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1584 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1585 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1591 adev->mes.fw_version[0] >= 99) { in gfx_v11_0_sw_init()
1606 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && in gfx_v11_0_sw_init()
1662 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1663 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1664 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1677 ring_id = 0; in gfx_v11_0_sw_init()
1679 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1680 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1681 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1682 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v11_0_sw_init()
1697 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v11_0_sw_init()
1699 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v11_0_sw_init()
1700 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1701 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1702 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1703 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1715 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); in gfx_v11_0_sw_init()
1726 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); in gfx_v11_0_sw_init()
1752 return 0; in gfx_v11_0_sw_init()
1789 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1791 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1794 amdgpu_gfx_mqd_sw_fini(adev, 0); in gfx_v11_0_sw_fini()
1797 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
1798 amdgpu_gfx_kiq_fini(adev, 0); in gfx_v11_0_sw_fini()
1819 return 0; in gfx_v11_0_sw_fini()
1827 if (instance == 0xffffffff) in gfx_v11_0_select_se_sh()
1828 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v11_0_select_se_sh()
1831 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v11_0_select_se_sh()
1834 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1840 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1846 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
1853 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1857 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1872 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1876 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1892 u32 active_rb_bitmap = 0; in gfx_v11_0_setup_rb()
1905 for (i = 0; i < max_sa; i++) { in gfx_v11_0_setup_rb()
1907 active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); in gfx_v11_0_setup_rb()
1915 #define DEFAULT_SH_MEM_BASES (0x6000)
1916 #define LDS_APP_BASE 0x1
1917 #define SCRATCH_APP_BASE 0x2
1927 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1928 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1929 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v11_0_init_compute_vmid()
1936 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_init_compute_vmid()
1938 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
1939 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
1942 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1944 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
1946 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_init_compute_vmid()
1954 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1955 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1956 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1957 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1972 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1973 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1974 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1975 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1987 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1988 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
2001 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
2006 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
2009 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
2016 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { in gfx_v11_0_constants_init()
2017 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_constants_init()
2019 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
2020 if (i != 0) { in gfx_v11_0_constants_init()
2021 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v11_0_constants_init()
2025 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
2028 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_constants_init()
2039 if (me != 0) in gfx_v11_0_get_cpg_int_cntl()
2040 return 0; in gfx_v11_0_get_cpg_int_cntl()
2043 case 0: in gfx_v11_0_get_cpg_int_cntl()
2044 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
2046 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_get_cpg_int_cntl()
2048 return 0; in gfx_v11_0_get_cpg_int_cntl()
2061 return 0; in gfx_v11_0_get_cpc_int_cntl()
2064 case 0: in gfx_v11_0_get_cpc_int_cntl()
2065 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2067 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2069 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2071 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2073 return 0; in gfx_v11_0_get_cpc_int_cntl()
2086 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_enable_gui_idle_interrupt()
2087 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
2093 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2095 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2097 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2099 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2110 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v11_0_init_csb()
2112 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v11_0_init_csb()
2113 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
2114 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
2116 return 0; in gfx_v11_0_init_csb()
2121 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2123 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
2124 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
2129 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2131 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2140 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2143 /* RLC_PG_CNTL[23] = 0 (default) in gfx_v11_0_rlc_smu_handshake_cntl()
2154 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
2164 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
2173 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v11_0_rlc_enable_srm()
2176 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v11_0_rlc_enable_srm()
2190 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v11_0_load_rlcg_microcode()
2193 for (i = 0; i < fw_size; i++) in gfx_v11_0_load_rlcg_microcode()
2194 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v11_0_load_rlcg_microcode()
2197 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
2213 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2215 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2218 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2222 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2228 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2229 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2232 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2236 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2238 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v11_0_load_rlc_iram_dram_microcode()
2240 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2241 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v11_0_load_rlc_iram_dram_microcode()
2257 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2259 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2262 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2266 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2268 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v11_0_load_rlcp_rlcv_microcode()
2270 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2276 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2278 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2281 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2285 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2287 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); in gfx_v11_0_load_rlcp_rlcv_microcode()
2289 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2316 return 0; in gfx_v11_0_rlc_load_microcode()
2334 return 0; in gfx_v11_0_rlc_resume()
2340 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
2343 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
2356 return 0; in gfx_v11_0_rlc_resume()
2366 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2368 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2371 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache()
2372 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2387 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache()
2388 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2389 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache()
2390 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache()
2392 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache()
2395 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache()
2396 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_me_cache()
2397 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2400 return 0; in gfx_v11_0_config_me_cache()
2410 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2412 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2415 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache()
2416 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2431 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2432 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2433 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache()
2434 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache()
2436 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2439 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache()
2440 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_pfp_cache()
2441 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache()
2444 return 0; in gfx_v11_0_config_pfp_cache()
2454 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2457 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2460 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache()
2461 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2476 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2477 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache()
2478 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache()
2480 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2483 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2484 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_mec_cache()
2485 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache()
2488 return 0; in gfx_v11_0_config_mec_cache()
2501 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache_rs64()
2503 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache_rs64()
2506 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2507 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2508 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2509 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache_rs64()
2510 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2517 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2518 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2531 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2533 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2535 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2536 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2549 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2550 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2551 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_pfp_cache_rs64()
2554 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_pfp_cache_rs64()
2561 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2562 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2568 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2571 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2573 PFP_PIPE0_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2576 PFP_PIPE1_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2577 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2579 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_config_pfp_cache_rs64()
2581 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_config_pfp_cache_rs64()
2584 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2587 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2588 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2589 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2590 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2593 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2595 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2597 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2598 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2610 return 0; in gfx_v11_0_config_pfp_cache_rs64()
2623 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache_rs64()
2625 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
2628 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2629 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2630 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2631 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache_rs64()
2632 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2639 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2640 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2653 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2655 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2658 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2659 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2672 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2673 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2674 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2677 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_me_cache_rs64()
2684 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2685 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2691 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2694 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2696 ME_PIPE0_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2699 ME_PIPE1_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2700 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2702 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_config_me_cache_rs64()
2704 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_config_me_cache_rs64()
2707 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2710 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2711 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2712 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2713 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2716 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2718 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2720 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2721 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2733 return 0; in gfx_v11_0_config_me_cache_rs64()
2746 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2747 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2748 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache_rs64()
2749 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2750 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2752 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2753 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2754 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2755 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2758 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2759 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2761 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); in gfx_v11_0_config_mec_cache_rs64()
2762 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2765 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
2768 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_mec_cache_rs64()
2771 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
2772 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2776 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2779 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2781 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2784 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2785 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2798 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2800 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2803 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2804 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2816 return 0; in gfx_v11_0_config_mec_cache_rs64()
2834 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2835 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2836 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2839 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2842 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2845 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2848 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2851 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2852 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2853 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2856 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2857 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2858 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2861 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2864 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2867 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2870 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2873 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2874 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2875 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2878 for (pipe_id = 0; pipe_id < 4; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2879 soc21_grbm_select(adev, 1, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2880 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2883 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2886 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2889 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
2894 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2897 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2898 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2899 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2900 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2901 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2911 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2912 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v11_0_wait_for_rlc_autoload_complete()
2914 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2915 IP_VERSION(11, 0, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2916 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2917 IP_VERSION(11, 0, 4) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2918 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2919 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2920 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2)) in gfx_v11_0_wait_for_rlc_autoload_complete()
2921 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
2924 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v11_0_wait_for_rlc_autoload_complete()
2926 if ((cp_status == 0) && in gfx_v11_0_wait_for_rlc_autoload_complete()
2981 return 0; in gfx_v11_0_wait_for_rlc_autoload_complete()
2987 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_enable()
2989 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
2990 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
2991 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
2993 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_cp_gfx_enable()
2994 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
3002 return 0; in gfx_v11_0_cp_gfx_enable()
3039 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3041 for (i = 0; i < pfp_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_pfp_microcode()
3042 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, in gfx_v11_0_cp_gfx_load_pfp_microcode()
3045 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3047 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode()
3111 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3113 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3116 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3117 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3118 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3119 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3120 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3127 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3128 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3141 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3143 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3145 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3146 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3159 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3160 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3161 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3164 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3171 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3172 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3178 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3181 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3183 PFP_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3186 PFP_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3187 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3189 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3191 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3194 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3197 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3198 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3199 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3200 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3203 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3205 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3207 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3208 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3220 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3257 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_me_microcode()
3259 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_me_microcode()
3260 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, in gfx_v11_0_cp_gfx_load_me_microcode()
3263 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
3265 return 0; in gfx_v11_0_cp_gfx_load_me_microcode()
3329 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3331 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3334 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3335 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3336 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3337 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3338 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3345 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3346 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3359 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3361 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3364 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3365 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3378 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3379 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3380 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3383 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3390 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3391 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3397 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3400 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3402 ME_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3405 ME_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3406 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3408 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3410 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3413 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3416 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3417 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3418 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3419 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3422 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3424 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3426 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3427 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3439 return 0; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3469 return 0; in gfx_v11_0_cp_gfx_load_microcode()
3481 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3483 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v11_0_cp_gfx_start()
3488 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3495 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3499 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3500 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3510 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_cp_gfx_start()
3517 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
3522 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3525 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3526 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3530 /* submit cs packet to copy state 0 to next available state */ in gfx_v11_0_cp_gfx_start()
3540 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3541 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3545 return 0; in gfx_v11_0_cp_gfx_start()
3553 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3556 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
3564 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_set_doorbell()
3572 DOORBELL_EN, 0); in gfx_v11_0_cp_gfx_set_doorbell()
3574 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3576 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_gfx_set_doorbell()
3578 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3580 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_gfx_set_doorbell()
3592 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v11_0_cp_gfx_resume()
3594 /* set the RB to use vmid 0 */ in gfx_v11_0_cp_gfx_resume()
3595 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
3597 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3602 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3604 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3606 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3609 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3610 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3611 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3615 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3616 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3620 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3622 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3626 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3629 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3630 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3632 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3644 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3646 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3648 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3649 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3650 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3653 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3654 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3657 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3659 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3663 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3666 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3667 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3668 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3673 /* Switch to pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3681 return 0; in gfx_v11_0_cp_gfx_resume()
3689 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3691 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3693 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3695 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3697 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3699 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3701 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3703 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3705 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3707 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3709 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3710 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
3712 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3715 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3718 MEC_ME2_HALT, 0); in gfx_v11_0_cp_compute_enable()
3723 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
3769 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3771 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v11_0_cp_compute_load_microcode()
3772 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, in gfx_v11_0_cp_compute_load_microcode()
3775 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3777 return 0; in gfx_v11_0_cp_compute_load_microcode()
3839 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3840 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3841 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3842 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3843 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3845 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3846 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3847 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3848 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3851 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3852 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3854 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3855 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3858 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
3861 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3864 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3865 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3869 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3872 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3874 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3877 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3878 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3891 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3893 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3896 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3897 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3909 return 0; in gfx_v11_0_cp_compute_load_microcode_rs64()
3918 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3919 tmp &= 0xffffff00; in gfx_v11_0_kiq_setting()
3921 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3922 tmp |= 0x80; in gfx_v11_0_kiq_setting()
3923 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in gfx_v11_0_kiq_setting()
3929 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3931 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3935 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3937 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3945 bool priority = 0; in gfx_v11_0_gfx_mqd_set_priority()
3949 * 0x0 = low priority, 0x1 = high priority in gfx_v11_0_gfx_mqd_set_priority()
3954 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); in gfx_v11_0_gfx_mqd_set_priority()
3968 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
3969 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
3972 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3976 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v11_0_gfx_mqd_init()
3977 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3979 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); in gfx_v11_0_gfx_mqd_init()
3982 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ in gfx_v11_0_gfx_mqd_init()
3983 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); in gfx_v11_0_gfx_mqd_init()
3984 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3985 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
3991 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); in gfx_v11_0_gfx_mqd_init()
4002 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4004 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4008 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4009 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4013 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); in gfx_v11_0_gfx_mqd_init()
4022 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_gfx_mqd_init()
4030 DOORBELL_EN, 0); in gfx_v11_0_gfx_mqd_init()
4034 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
4039 return 0; in gfx_v11_0_gfx_mqd_init()
4046 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_kgq_init_queue()
4049 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4051 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kgq_init_queue()
4053 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kgq_init_queue()
4062 ring->wptr = 0; in gfx_v11_0_kgq_init_queue()
4063 *ring->wptr_cpu_addr = 0; in gfx_v11_0_kgq_init_queue()
4067 return 0; in gfx_v11_0_kgq_init_queue()
4075 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
4079 if (unlikely(r != 0)) in gfx_v11_0_cp_async_gfx_ring_resume()
4093 r = amdgpu_gfx_enable_kgq(adev, 0); in gfx_v11_0_cp_async_gfx_ring_resume()
4107 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
4108 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
4109 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4110 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4111 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4112 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4113 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
4120 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); in gfx_v11_0_compute_mqd_init()
4127 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4135 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4137 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4140 DOORBELL_EN, 0); in gfx_v11_0_compute_mqd_init()
4146 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
4147 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
4148 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
4149 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
4152 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4155 /* set MQD vmid to 0 */ in gfx_v11_0_compute_mqd_init()
4156 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in gfx_v11_0_compute_mqd_init()
4157 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()
4166 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
4180 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4182 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4186 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4187 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4189 tmp = 0; in gfx_v11_0_compute_mqd_init()
4192 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4199 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4201 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4207 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
4210 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
4212 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); in gfx_v11_0_compute_mqd_init()
4213 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); in gfx_v11_0_compute_mqd_init()
4217 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); in gfx_v11_0_compute_mqd_init()
4227 return 0; in gfx_v11_0_compute_mqd_init()
4238 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4241 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4244 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4246 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4250 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
4254 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4258 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4259 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
4260 for (j = 0; j < adev->usec_timeout; j++) { in gfx_v11_0_kiq_init_register()
4261 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4265 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
4267 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
4269 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4271 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4276 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4278 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4281 /* set MQD vmid to 0 */ in gfx_v11_0_kiq_init_register()
4282 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
4286 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
4288 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v11_0_kiq_init_register()
4292 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
4296 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
4298 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v11_0_kiq_init_register()
4302 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
4304 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
4309 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_kiq_init_register()
4311 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_kiq_init_register()
4315 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4321 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4325 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4327 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v11_0_kiq_init_register()
4331 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
4335 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
4337 return 0; in gfx_v11_0_kiq_init_register()
4349 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4350 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4353 ring->wptr = 0; in gfx_v11_0_kiq_init_queue()
4357 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4359 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4362 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4366 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4369 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4372 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4373 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4376 return 0; in gfx_v11_0_kiq_init_queue()
4383 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4386 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4388 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kcq_init_queue()
4390 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kcq_init_queue()
4400 ring->wptr = 0; in gfx_v11_0_kcq_init_queue()
4401 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); in gfx_v11_0_kcq_init_queue()
4405 return 0; in gfx_v11_0_kcq_init_queue()
4413 ring = &adev->gfx.kiq[0].ring; in gfx_v11_0_kiq_resume()
4416 if (unlikely(r != 0)) in gfx_v11_0_kiq_resume()
4420 if (unlikely(r != 0)) { in gfx_v11_0_kiq_resume()
4430 return 0; in gfx_v11_0_kiq_resume()
4436 int r = 0, i; in gfx_v11_0_kcq_resume()
4441 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4445 if (unlikely(r != 0)) in gfx_v11_0_kcq_resume()
4458 r = amdgpu_gfx_enable_kcq(adev, 0); in gfx_v11_0_kcq_resume()
4513 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4520 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4527 return 0; in gfx_v11_0_cp_resume()
4553 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); in gfx_v11_0_gfxhub_enable()
4555 return 0; in gfx_v11_0_gfxhub_enable()
4564 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); in gfx_v11_0_select_cp_fw_arch()
4566 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4568 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); in gfx_v11_0_select_cp_fw_arch()
4570 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4581 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4582 if (gb_addr_config == 0) in get_gb_addr_config()
4610 return 0; in get_gb_addr_config()
4617 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4619 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4621 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4623 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4646 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4721 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); in gfx_v11_0_hw_init()
4730 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4731 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4732 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_hw_fini()
4736 if (amdgpu_gfx_disable_kgq(adev, 0)) in gfx_v11_0_hw_fini()
4740 if (amdgpu_gfx_disable_kcq(adev, 0)) in gfx_v11_0_hw_fini()
4752 return 0; in gfx_v11_0_hw_fini()
4761 return 0; in gfx_v11_0_hw_fini()
4778 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v11_0_is_idle()
4791 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_idle()
4793 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v11_0_wait_for_idle()
4797 return 0; in gfx_v11_0_wait_for_idle()
4808 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_request_gfx_index_mutex()
4809 /* Request with MeId=2, PipeId=0 */ in gfx_v11_0_request_gfx_index_mutex()
4810 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); in gfx_v11_0_request_gfx_index_mutex()
4812 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); in gfx_v11_0_request_gfx_index_mutex()
4814 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); in gfx_v11_0_request_gfx_index_mutex()
4832 return 0; in gfx_v11_0_request_gfx_index_mutex()
4837 u32 grbm_soft_reset = 0; in gfx_v11_0_soft_reset()
4842 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4844 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4845 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4846 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4847 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4848 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4849 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4852 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4853 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4854 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4855 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4857 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
4858 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
4862 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4863 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4864 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4865 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4867 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); in gfx_v11_0_soft_reset()
4871 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_soft_reset()
4883 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
4886 // to get sufficient time for GFX_HQD_ACTIVE reach 0 in gfx_v11_0_soft_reset()
4887 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4888 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4889 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4899 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4900 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
4901 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) in gfx_v11_0_soft_reset()
4911 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4922 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4924 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4926 SOFT_RESET_CP, 0); in gfx_v11_0_soft_reset()
4928 SOFT_RESET_GFX, 0); in gfx_v11_0_soft_reset()
4930 SOFT_RESET_CPF, 0); in gfx_v11_0_soft_reset()
4932 SOFT_RESET_CPC, 0); in gfx_v11_0_soft_reset()
4934 SOFT_RESET_CPG, 0); in gfx_v11_0_soft_reset()
4935 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4937 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); in gfx_v11_0_soft_reset()
4938 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); in gfx_v11_0_soft_reset()
4939 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); in gfx_v11_0_soft_reset()
4941 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); in gfx_v11_0_soft_reset()
4942 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
4944 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4945 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
4950 printk("Failed to wait CP_VMID_RESET to 0\n"); in gfx_v11_0_soft_reset()
4954 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4959 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4961 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4973 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4980 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
5007 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5008 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5009 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5011 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5016 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
5017 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
5018 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
5020 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
5037 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5038 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5042 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5043 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5047 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5048 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5052 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5053 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5085 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
5089 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5093 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_late_init()
5096 return 0; in gfx_v11_0_late_init()
5104 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
5116 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v11_0_set_safe_mode()
5119 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_set_safe_mode()
5120 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v11_0_set_safe_mode()
5129 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
5140 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_perf_clk()
5148 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_perf_clk()
5159 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_sram_fgcg()
5167 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_sram_fgcg()
5178 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_repeater_fgcg()
5186 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_repeater_fgcg()
5201 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5208 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5212 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5219 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5237 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_coarse_grain_clock_gating()
5250 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5252 /* enable cgcg FSM(0x0000363F) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5253 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5257 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5263 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5268 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5271 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5275 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5281 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5286 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5288 /* set IDLE_POLL_COUNT(0x00900100) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5289 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5292 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5293 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v11_0_update_coarse_grain_clock_gating()
5296 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5298 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5303 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5305 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5307 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5311 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5313 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5317 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5326 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5329 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5337 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5339 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5341 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5345 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5347 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5355 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5375 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5377 return 0; in gfx_v11_0_update_gfx_clock_gating()
5385 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
5396 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5398 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5427 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5434 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
5438 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_cntl_power_gating()
5439 case IP_VERSION(11, 0, 1): in gfx_v11_cntl_power_gating()
5440 case IP_VERSION(11, 0, 4): in gfx_v11_cntl_power_gating()
5441 case IP_VERSION(11, 5, 0): in gfx_v11_cntl_power_gating()
5444 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); in gfx_v11_cntl_power_gating()
5454 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5458 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5468 return 0; in gfx_v11_0_set_powergating_state()
5470 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_powergating_state()
5471 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_powergating_state()
5472 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_powergating_state()
5473 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_powergating_state()
5476 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_powergating_state()
5477 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_powergating_state()
5478 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_powergating_state()
5494 return 0; in gfx_v11_0_set_powergating_state()
5503 return 0; in gfx_v11_0_set_clockgating_state()
5505 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_clockgating_state()
5506 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_clockgating_state()
5507 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_clockgating_state()
5508 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_clockgating_state()
5509 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_clockgating_state()
5510 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_clockgating_state()
5511 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_clockgating_state()
5521 return 0; in gfx_v11_0_set_clockgating_state()
5530 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_get_clockgating_state()
5547 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
5556 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
5580 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5581 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5597 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
5599 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
5653 reg_mem_engine = 0; in gfx_v11_0_ring_emit_hdp_flush()
5659 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, in gfx_v11_0_ring_emit_hdp_flush()
5662 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
5671 u32 header, control = 0; in gfx_v11_0_ring_emit_ib_gfx()
5692 control |= 0x400000; in gfx_v11_0_ring_emit_ib_gfx()
5695 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_gfx()
5698 (2 << 0) | in gfx_v11_0_ring_emit_ib_gfx()
5715 control |= 0x40000000; in gfx_v11_0_ring_emit_ib_compute()
5725 * GDS to 0 for this ring (me/pipe). in gfx_v11_0_ring_emit_ib_compute()
5734 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_compute()
5737 (2 << 0) | in gfx_v11_0_ring_emit_ib_compute()
5760 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
5767 BUG_ON(addr & 0x7); in gfx_v11_0_ring_emit_fence()
5769 BUG_ON(addr & 0x3); in gfx_v11_0_ring_emit_fence()
5775 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); in gfx_v11_0_ring_emit_fence()
5784 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), in gfx_v11_0_ring_emit_pipeline_sync()
5785 upper_32_bits(addr), seq, 0xffffffff, 4); in gfx_v11_0_ring_emit_pipeline_sync()
5792 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v11_0_ring_invalidate_tlbs()
5804 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); in gfx_v11_0_ring_emit_vm_flush()
5811 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v11_0_ring_emit_vm_flush()
5812 amdgpu_ring_write(ring, 0x0); in gfx_v11_0_ring_emit_vm_flush()
5818 ring->set_q_mode_offs = 0; in gfx_v11_0_ring_emit_vm_flush()
5832 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5841 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5842 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5843 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()
5844 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_fence_kiq()
5845 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ in gfx_v11_0_ring_emit_fence_kiq()
5852 uint32_t dw2 = 0; in gfx_v11_0_ring_emit_cntxcntl()
5854 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v11_0_ring_emit_cntxcntl()
5857 dw2 |= 0x8001; in gfx_v11_0_ring_emit_cntxcntl()
5859 dw2 |= 0x01000000; in gfx_v11_0_ring_emit_cntxcntl()
5861 dw2 |= 0x10002; in gfx_v11_0_ring_emit_cntxcntl()
5866 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_cntxcntl()
5877 /* discard following DWs if *cond_exec_gpu_addr==0 */ in gfx_v11_0_ring_emit_init_cond_exec()
5878 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5881 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5917 amdgpu_ring_write(ring, shadow_va ? 1 : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5918 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_gfx_shadow()
5941 amdgpu_ring_write(ring, 0x1); in gfx_v11_0_ring_emit_gfx_shadow()
5952 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5954 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5967 *ring->set_q_mode_ptr = 0; in gfx_v11_0_ring_emit_gfx_shadow()
5979 int i, r = 0; in gfx_v11_0_ring_preempt_ib()
5981 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v11_0_ring_preempt_ib()
6010 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_preempt_ib()
6030 struct v10_de_ib_state de_payload = {0}; in gfx_v11_0_ring_emit_de_meta()
6037 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
6045 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
6066 WRITE_DATA_CACHE_POLICY(0)); in gfx_v11_0_ring_emit_de_meta()
6081 uint32_t v = secure ? FRAME_TMZ : 0; in gfx_v11_0_ring_emit_frame_cntl()
6083 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); in gfx_v11_0_ring_emit_frame_cntl()
6084 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); in gfx_v11_0_ring_emit_frame_cntl()
6093 amdgpu_ring_write(ring, 0 | /* src: register*/ in gfx_v11_0_ring_emit_rreg()
6097 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_rreg()
6107 uint32_t cmd = 0; in gfx_v11_0_ring_emit_wreg()
6123 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_wreg()
6130 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); in gfx_v11_0_ring_emit_reg_wait()
6139 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, in gfx_v11_0_ring_emit_reg_write_reg_wait()
6140 ref, mask, 0x20); in gfx_v11_0_ring_emit_reg_write_reg_wait()
6147 uint32_t value = 0; in gfx_v11_0_ring_soft_recovery()
6149 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v11_0_ring_soft_recovery()
6150 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v11_0_ring_soft_recovery()
6153 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6154 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v11_0_ring_soft_recovery()
6155 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6167 case 0: in gfx_v11_0_set_gfx_eop_interrupt_state()
6168 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6171 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6186 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6188 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6218 case 0: in gfx_v11_0_set_compute_eop_interrupt_state()
6219 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6222 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6225 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6228 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6243 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6245 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6268 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6271 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); in gfx_v11_0_set_eop_interrupt_state()
6274 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6288 return 0; in gfx_v11_0_set_eop_interrupt_state()
6298 uint32_t mes_queue_id = entry->src_data[0]; in gfx_v11_0_eop_irq()
6315 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_eop_irq()
6316 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_eop_irq()
6317 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_eop_irq()
6320 case 0: in gfx_v11_0_eop_irq()
6321 if (pipe_id == 0) in gfx_v11_0_eop_irq()
6322 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
6328 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
6343 return 0; in gfx_v11_0_eop_irq()
6357 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6358 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6365 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6370 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6371 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6379 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6389 return 0; in gfx_v11_0_set_priv_reg_fault_state()
6403 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_bad_op_fault_state()
6404 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
6411 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6416 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6417 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_bad_op_fault_state()
6425 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6434 return 0; in gfx_v11_0_set_bad_op_fault_state()
6448 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_inst_fault_state()
6449 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_inst_fault_state()
6456 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
6466 return 0; in gfx_v11_0_set_priv_inst_fault_state()
6476 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_handle_priv_fault()
6477 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_handle_priv_fault()
6478 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_handle_priv_fault()
6481 case 0: in gfx_v11_0_handle_priv_fault()
6482 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
6491 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
6510 return 0; in gfx_v11_0_priv_reg_irq()
6519 return 0; in gfx_v11_0_bad_op_irq()
6528 return 0; in gfx_v11_0_priv_inst_irq()
6538 return 0; in gfx_v11_0_rlc_gc_fed_irq()
6541 #if 0
6548 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6550 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6556 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6558 GENERIC2_INT_ENABLE, 0);
6559 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6563 GENERIC2_INT_ENABLE, 0);
6566 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6569 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6581 return 0;
6599 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ in gfx_v11_0_emit_mem_sync()
6600 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v11_0_emit_mem_sync()
6601 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx_v11_0_emit_mem_sync()
6602 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v11_0_emit_mem_sync()
6603 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v11_0_emit_mem_sync()
6604 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ in gfx_v11_0_emit_mem_sync()
6621 if (unlikely(r != 0)) { in gfx_v11_0_reset_kgq()
6649 int i, r = 0; in gfx_v11_0_reset_kcq()
6654 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_reset_kcq()
6656 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_reset_kcq()
6657 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_reset_kcq()
6658 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_reset_kcq()
6661 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_reset_kcq()
6662 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_reset_kcq()
6668 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_reset_kcq()
6670 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_reset_kcq()
6677 if (unlikely(r != 0)) { in gfx_v11_0_reset_kcq()
6704 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_print()
6710 for (i = 0; i < reg_count; i++) in gfx_v11_ip_print()
6711 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6725 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
6726 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_print()
6727 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6729 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6730 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6743 index = 0; in gfx_v11_ip_print()
6750 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_print()
6751 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
6752 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6754 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6755 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6768 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_dump()
6775 for (i = 0; i < reg_count; i++) in gfx_v11_ip_dump()
6786 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_dump()
6787 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_dump()
6788 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6790 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v11_ip_dump()
6791 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6800 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6808 index = 0; in gfx_v11_ip_dump()
6812 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_dump()
6813 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_dump()
6814 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6815 soc21_grbm_select(adev, i, j, k, 0); in gfx_v11_ip_dump()
6817 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6826 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6834 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); in gfx_v11_0_ring_emit_cleaner_shader()
6835 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ in gfx_v11_0_ring_emit_cleaner_shader()
6862 .align_mask = 0xff,
6863 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6918 .align_mask = 0xff,
6919 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6960 .align_mask = 0xff,
6961 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6991 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6993 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6996 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
7038 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ in gfx_v11_0_set_irq_funcs()
7064 adev->gds.gds_size = 0x1000; in gfx_v11_0_set_gds_init()
7095 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
7101 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7102 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7119 cu_active_bitmap = 0; in gfx_v11_0_get_cu_active_bitmap_per_sh()
7121 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { in gfx_v11_0_get_cu_active_bitmap_per_sh()
7134 int i, j, k, counter, active_cu_number = 0; in gfx_v11_0_get_cu_info()
7144 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
7145 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7150 counter = 0; in gfx_v11_0_get_cu_info()
7151 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7163 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} in gfx_v11_0_get_cu_info()
7164 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} in gfx_v11_0_get_cu_info()
7165 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} in gfx_v11_0_get_cu_info()
7166 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} in gfx_v11_0_get_cu_info()
7167 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} in gfx_v11_0_get_cu_info()
7172 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; in gfx_v11_0_get_cu_info()
7174 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()
7183 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7189 return 0; in gfx_v11_0_get_cu_info()
7196 .minor = 0,
7197 .rev = 0,