Lines Matching refs:rlc
4049 kfree(adev->gfx.rlc.register_list_format);
4240 if (adev->gfx.rlc.cs_data == NULL)
4252 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4283 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4284 &adev->gfx.rlc.clear_state_gpu_addr,
4285 (void **)&adev->gfx.rlc.cs_ptr);
4288 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4289 &adev->gfx.rlc.cp_table_gpu_addr,
4290 (void **)&adev->gfx.rlc.cp_table_ptr);
4297 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4314 adev->gfx.rlc.rlcg_reg_access_supported = true;
4322 adev->gfx.rlc.cs_data = gfx10_cs_data;
4324 cs_data = adev->gfx.rlc.cs_data;
4767 if (adev->gfx.rlc.funcs) {
4768 if (adev->gfx.rlc.funcs->init) {
4769 r = adev->gfx.rlc.funcs->init(adev);
4771 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4832 /* allocate visible FB for rlc auto-loading fw */
5295 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5300 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5302 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5303 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5306 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5308 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5309 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5355 * TODO: enable rlc & smu handshake until smu
5427 adev->gfx.rlc.funcs->stop(adev);
5436 /* legacy rlc firmware loading */
5441 /* rlc backdoor autoload firmware */
5451 adev->gfx.rlc.funcs->start(adev);
5476 &adev->gfx.rlc.rlc_toc_bo,
5477 &adev->gfx.rlc.rlc_toc_gpu_addr,
5478 (void **)&adev->gfx.rlc.rlc_toc_buf);
5480 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5484 /* Copy toc from psp sos fw to rlc toc buffer */
5485 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5487 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5514 dev_err(adev->dev, "failed to parse rlc toc\n");
5521 /* In case the offset in rlc toc ucode is aligned */
5538 &adev->gfx.rlc.rlc_autoload_bo,
5539 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5540 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5551 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5552 &adev->gfx.rlc.rlc_toc_gpu_addr,
5553 (void **)&adev->gfx.rlc.rlc_toc_buf);
5554 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5555 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5556 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5566 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5591 data = adev->gfx.rlc.rlc_toc_buf;
5636 /* rlc ucode */
5705 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5754 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5791 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5828 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5865 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5893 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
7379 * For gfx 10, rlc firmware loading relies on smu firmware is
7381 * here before rlc.
7400 * init golden registers and rlc resume may override some registers,
7551 /* stop the rlc */
9913 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9917 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;