4350 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);  in gfx_v10_0_mec_fini()
4351 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);  in gfx_v10_0_mec_fini()
4381 					      &adev->gfx.mec.hpd_eop_obj,  in gfx_v10_0_mec_init()
4382 					      &adev->gfx.mec.hpd_eop_gpu_addr,  in gfx_v10_0_mec_init()
4392 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);  in gfx_v10_0_mec_init()
4393 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v10_0_mec_init()
4405 					      &adev->gfx.mec.mec_fw_obj,  in gfx_v10_0_mec_init()
4406 					      &adev->gfx.mec.mec_fw_gpu_addr,  in gfx_v10_0_mec_init()
4416 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);  in gfx_v10_0_mec_init()
4417 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);  in gfx_v10_0_mec_init()
4626 				       int mec, int pipe, int queue)  in gfx_v10_0_compute_ring_init()  argument
4635 	ring->me = mec + 1;  in gfx_v10_0_compute_ring_init()
4642 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr  in gfx_v10_0_compute_ring_init()
4648 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)  in gfx_v10_0_compute_ring_init()
4673 	inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *  in gfx_v10_0_alloc_ip_dump()
4674 		adev->gfx.mec.num_queue_per_pipe;  in gfx_v10_0_alloc_ip_dump()
4713 		adev->gfx.mec.num_mec = 2;  in gfx_v10_0_sw_init()
4714 		adev->gfx.mec.num_pipe_per_mec = 4;  in gfx_v10_0_sw_init()
4715 		adev->gfx.mec.num_queue_per_pipe = 8;  in gfx_v10_0_sw_init()
4728 		adev->gfx.mec.num_mec = 2;  in gfx_v10_0_sw_init()
4729 		adev->gfx.mec.num_pipe_per_mec = 4;  in gfx_v10_0_sw_init()
4730 		adev->gfx.mec.num_queue_per_pipe = 4;  in gfx_v10_0_sw_init()
4736 		adev->gfx.mec.num_mec = 1;  in gfx_v10_0_sw_init()
4737 		adev->gfx.mec.num_pipe_per_mec = 4;  in gfx_v10_0_sw_init()
4738 		adev->gfx.mec.num_queue_per_pipe = 8;  in gfx_v10_0_sw_init()
4835 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {  in gfx_v10_0_sw_init()
4836 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {  in gfx_v10_0_sw_init()
4837 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {  in gfx_v10_0_sw_init()
6585 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &  in gfx_v10_0_cp_compute_load_microcode()
6588 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));  in gfx_v10_0_cp_compute_load_microcode()
7089 		if (adev->gfx.mec.mqd_backup[mqd_idx])  in gfx_v10_0_kcq_init_queue()
7090 			memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));  in gfx_v10_0_kcq_init_queue()
7093 		if (adev->gfx.mec.mqd_backup[mqd_idx])  in gfx_v10_0_kcq_init_queue()
7094 			memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));  in gfx_v10_0_kcq_init_queue()
9203 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v10_0_set_priv_reg_fault_state()
9204 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v10_0_set_priv_reg_fault_state()
9249 		for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v10_0_set_bad_op_fault_state()
9250 			for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v10_0_set_bad_op_fault_state()
9633 		   adev->gfx.mec.num_mec,  in gfx_v10_ip_print()
9634 		   adev->gfx.mec.num_pipe_per_mec,  in gfx_v10_ip_print()
9635 		   adev->gfx.mec.num_queue_per_pipe);  in gfx_v10_ip_print()
9637 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v10_ip_print()
9638 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v10_ip_print()
9639 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {  in gfx_v10_ip_print()
9698 	for (i = 0; i < adev->gfx.mec.num_mec; i++) {  in gfx_v10_ip_dump()
9699 		for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {  in gfx_v10_ip_dump()
9700 			for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {  in gfx_v10_ip_dump()