89 	uint32_t	hpd;  member
95 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
100 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
105 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
110 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
115 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
120 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
229 			       enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_sense()  argument
233 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_sense()
236 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &  in dce_v8_0_hpd_sense()
252 				      enum amdgpu_hpd_id hpd)  in dce_v8_0_hpd_set_polarity()  argument
255 	bool connected = dce_v8_0_hpd_sense(adev, hpd);  in dce_v8_0_hpd_set_polarity()
257 	if (hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_set_polarity()
260 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_set_polarity()
265 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_set_polarity()
269 				 int hpd)  in dce_v8_0_hpd_int_ack()  argument
273 	if (hpd >= adev->mode_info.num_hpd) {  in dce_v8_0_hpd_int_ack()
274 		DRM_DEBUG("invalid hdp %d\n", hpd);  in dce_v8_0_hpd_int_ack()
278 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);  in dce_v8_0_hpd_int_ack()
280 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);  in dce_v8_0_hpd_int_ack()
302 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_init()
305 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
307 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
316 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_init()
318 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_init()
322 		dce_v8_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
323 		dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
324 		amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_init()
348 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)  in dce_v8_0_hpd_fini()
351 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);  in dce_v8_0_hpd_fini()
353 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);  in dce_v8_0_hpd_fini()
355 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);  in dce_v8_0_hpd_fini()
3220 	unsigned hpd;  in dce_v8_0_hpd_irq()  local
3227 	hpd = entry->src_data[0];  in dce_v8_0_hpd_irq()
3228 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);  in dce_v8_0_hpd_irq()
3229 	mask = interrupt_status_offsets[hpd].hpd;  in dce_v8_0_hpd_irq()
3232 		dce_v8_0_hpd_int_ack(adev, hpd);  in dce_v8_0_hpd_irq()
3234 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);  in dce_v8_0_hpd_irq()