Lines Matching +full:hdr +full:- +full:engine
76 for (i = 0; i < adev->sdma.num_instances; i++)
77 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
81 * sDMA - System DMA
98 * cik_sdma_init_microcode - load ucode images from disk
113 switch (adev->asic_type) {
132 for (i = 0; i < adev->sdma.num_instances; i++) {
134 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
138 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw,
148 for (i = 0; i < adev->sdma.num_instances; i++)
149 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
155 * cik_sdma_ring_get_rptr - get the current read pointer
165 rptr = *ring->rptr_cpu_addr;
171 * cik_sdma_ring_get_wptr - get the current write pointer
179 struct amdgpu_device *adev = ring->adev;
181 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
185 * cik_sdma_ring_set_wptr - commit the write pointer
193 struct amdgpu_device *adev = ring->adev;
195 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
196 (ring->wptr << 2) & 0x3fffc);
205 if (sdma && sdma->burst_nop && (i == 0))
206 amdgpu_ring_write(ring, ring->funcs->nop |
207 SDMA_NOP_COUNT(count - 1));
209 amdgpu_ring_write(ring, ring->funcs->nop);
213 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
231 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
236 amdgpu_ring_write(ring, ib->length_dw);
241 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
253 if (ring->me == 0)
267 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
302 * cik_sdma_gfx_stop - stop the gfx async dma engines
313 for (i = 0; i < adev->sdma.num_instances; i++) {
322 * cik_sdma_rlc_stop - stop the compute async dma engines
334 * cik_ctx_switch_enable - stop the async dma engines context switch
370 for (i = 0; i < adev->sdma.num_instances; i++) {
391 * cik_sdma_enable - stop the async dma engines
408 for (i = 0; i < adev->sdma.num_instances; i++) {
419 * cik_sdma_gfx_resume - setup and start the async dma engines
433 for (i = 0; i < adev->sdma.num_instances; i++) {
434 ring = &adev->sdma.instance[i].ring;
436 mutex_lock(&adev->srbm_mutex);
442 /* XXX SDMA RLC - todo */
445 mutex_unlock(&adev->srbm_mutex);
448 adev->gfx.config.gb_addr_config & 0x70);
454 rb_bufsz = order_base_2(ring->ring_size / 4);
470 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
472 ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
476 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
477 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
479 ring->wptr = 0;
480 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
496 for (i = 0; i < adev->sdma.num_instances; i++) {
497 ring = &adev->sdma.instance[i].ring;
507 * cik_sdma_rlc_resume - setup and start the async dma engines
521 * cik_sdma_load_microcode - load the sDMA ME ucode
526 * Returns 0 for success, -EINVAL if the ucode is not available.
530 const struct sdma_firmware_header_v1_0 *hdr;
538 for (i = 0; i < adev->sdma.num_instances; i++) {
539 if (!adev->sdma.instance[i].fw)
540 return -EINVAL;
541 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
542 amdgpu_ucode_print_sdma_hdr(&hdr->header);
543 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
544 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
545 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
546 if (adev->sdma.instance[i].feature_version >= 20)
547 adev->sdma.instance[i].burst_nop = true;
549 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
553 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
560 * cik_sdma_start - setup and start the async dma engines
575 /* halt the engine before programing */
592 * cik_sdma_ring_test_ring - simple async dma engine test
596 * Test the DMA engine by writing using it to write an
602 struct amdgpu_device *adev = ring->adev;
613 gpu_addr = adev->wb.gpu_addr + (index * 4);
615 adev->wb.wb[index] = cpu_to_le32(tmp);
628 for (i = 0; i < adev->usec_timeout; i++) {
629 tmp = le32_to_cpu(adev->wb.wb[index]);
635 if (i >= adev->usec_timeout)
636 r = -ETIMEDOUT;
644 * cik_sdma_ring_test_ib - test an IB on the DMA engine
654 struct amdgpu_device *adev = ring->adev;
666 gpu_addr = adev->wb.gpu_addr + (index * 4);
668 adev->wb.wb[index] = cpu_to_le32(tmp);
688 r = -ETIMEDOUT;
693 tmp = le32_to_cpu(adev->wb.wb[index]);
697 r = -EINVAL;
708 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
723 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
725 ib->ptr[ib->length_dw++] = bytes;
726 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
727 ib->ptr[ib->length_dw++] = lower_32_bits(src);
728 ib->ptr[ib->length_dw++] = upper_32_bits(src);
729 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
730 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
734 * cik_sdma_vm_write_pte - update PTEs by writing them manually
750 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
752 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
753 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
754 ib->ptr[ib->length_dw++] = ndw;
755 for (; ndw > 0; ndw -= 2) {
756 ib->ptr[ib->length_dw++] = lower_32_bits(value);
757 ib->ptr[ib->length_dw++] = upper_32_bits(value);
763 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
779 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
780 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
781 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
782 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
783 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
784 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
785 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
786 ib->ptr[ib->length_dw++] = incr; /* increment size */
787 ib->ptr[ib->length_dw++] = 0;
788 ib->ptr[ib->length_dw++] = count; /* number of entries */
792 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
804 pad_count = (-ib->length_dw) & 7;
806 if (sdma && sdma->burst_nop && (i == 0))
807 ib->ptr[ib->length_dw++] =
809 SDMA_NOP_COUNT(pad_count - 1);
811 ib->ptr[ib->length_dw++] =
816 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
824 uint32_t seq = ring->fence_drv.sync_seq;
825 uint64_t addr = ring->fence_drv.gpu_addr;
840 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
878 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
899 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
924 struct amdgpu_device *adev = ip_block->adev;
927 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
944 struct amdgpu_device *adev = ip_block->adev;
949 &adev->sdma.trap_irq);
955 &adev->sdma.illegal_inst_irq);
961 &adev->sdma.illegal_inst_irq);
965 for (i = 0; i < adev->sdma.num_instances; i++) {
966 ring = &adev->sdma.instance[i].ring;
967 ring->ring_obj = NULL;
968 sprintf(ring->name, "sdma%d", i);
970 &adev->sdma.trap_irq,
983 struct amdgpu_device *adev = ip_block->adev;
986 for (i = 0; i < adev->sdma.num_instances; i++)
987 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
995 struct amdgpu_device *adev = ip_block->adev;
1002 struct amdgpu_device *adev = ip_block->adev;
1024 struct amdgpu_device *adev = ip_block->adev;
1037 struct amdgpu_device *adev = ip_block->adev;
1039 for (i = 0; i < adev->usec_timeout; i++) {
1044 return -ETIMEDOUT;
1050 struct amdgpu_device *adev = ip_block->adev;
1068 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1137 instance_id = (entry->ring_id & 0x3) >> 0;
1138 queue_id = (entry->ring_id & 0xc) >> 2;
1144 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1157 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1179 instance_id = (entry->ring_id & 0x3) >> 0;
1180 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1188 struct amdgpu_device *adev = ip_block->adev;
1252 for (i = 0; i < adev->sdma.num_instances; i++) {
1253 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1254 adev->sdma.instance[i].ring.me = i;
1269 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1270 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1271 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1275 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1283 * Copy GPU buffers using the DMA engine (CIK).
1293 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1294 ib->ptr[ib->length_dw++] = byte_count;
1295 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1296 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1297 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1298 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1299 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1303 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1310 * Fill GPU buffers using the DMA engine (CIK).
1317 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1318 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1319 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1320 ib->ptr[ib->length_dw++] = src_data;
1321 ib->ptr[ib->length_dw++] = byte_count;
1336 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1337 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1352 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1353 for (i = 0; i < adev->sdma.num_instances; i++) {
1354 adev->vm_manager.vm_pte_scheds[i] =
1355 &adev->sdma.instance[i].ring.sched;
1357 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;