38  * Starting with r6xx, interrupts are handled via a ring buffer.
45  * writes vectors to the ring buffer, it increments the
54  * cik_ih_enable_interrupts - Enable the interrupt ring buffer
58  * Enable the interrupt ring buffer (CIK).
69 	adev->irq.ih.enabled = true;  in cik_ih_enable_interrupts()
73  * cik_ih_disable_interrupts - Disable the interrupt ring buffer
77  * Disable the interrupt ring buffer (CIK).
91 	adev->irq.ih.enabled = false;  in cik_ih_disable_interrupts()
92 	adev->irq.ih.rptr = 0;  in cik_ih_disable_interrupts()
96  * cik_ih_irq_init - init and enable the interrupt ring
100  * Allocate a ring buffer for the interrupt controller,
101  * enable the RLC, disable interrupts, enable the IH
102  * ring buffer and enable it (CIK).
108 	struct amdgpu_ih_ring *ih = &adev->irq.ih;  in cik_ih_irq_init()
116 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);  in cik_ih_irq_init()
118 	/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi  in cik_ih_irq_init()
119 	 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN  in cik_ih_irq_init()
122 	/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */  in cik_ih_irq_init()
126 	WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in cik_ih_irq_init()
127 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in cik_ih_irq_init()
136 	WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));  in cik_ih_irq_init()
137 	WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF);  in cik_ih_irq_init()
150 	if (adev->irq.msi_enabled)  in cik_ih_irq_init()
154 	pci_set_master(adev->pdev);  in cik_ih_irq_init()
156 	/* enable irqs */  in cik_ih_irq_init()
159 	if (adev->irq.ih_soft.ring_size)  in cik_ih_irq_init()
160 		adev->irq.ih_soft.enabled = true;  in cik_ih_irq_init()
166  * cik_ih_irq_disable - disable interrupts
180  * cik_ih_get_wptr - get the IH ring buffer wptr
183  * @ih: IH ring buffer to fetch wptr
185  * Get the IH ring buffer wptr from either the register
186  * or the writeback memory buffer (CIK).  Also check for
187  * ring buffer overflow and deal with it.
196 	wptr = le32_to_cpu(*ih->wptr_cpu);  in cik_ih_get_wptr()
198 	if (ih == &adev->irq.ih_soft)  in cik_ih_get_wptr()
203 		/* When a ring buffer overflow happen start parsing interrupt  in cik_ih_get_wptr()
207 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in cik_ih_get_wptr()
208 			 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask);  in cik_ih_get_wptr()
209 		ih->rptr = (wptr + 16) & ih->ptr_mask;  in cik_ih_get_wptr()
222 	return (wptr & ih->ptr_mask);  in cik_ih_get_wptr()
227  * [7:0]    - interrupt source id
228  * [31:8]   - reserved
229  * [59:32]  - interrupt source data
230  * [63:60]  - reserved
231  * [71:64]  - RINGID
234  *            QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
235  *                     - for gfx, hw shader state (0=PS...5=LS, 6=CS)
236  *            ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
237  *            PIPE_ID - ME0 0=3D
238  *                    - ME1&2 compute dispatcher (4 pipes each)
241  *            INSTANCE_ID - 0 = sdma0, 1 = sdma1
242  *            QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
243  * [79:72]  - VMID
244  * [95:80]  - PASID
245  * [127:96] - reserved
249  * cik_ih_decode_iv - decode an interrupt vector
261 	u32 ring_index = ih->rptr >> 2;  in cik_ih_decode_iv()
264 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);  in cik_ih_decode_iv()
265 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);  in cik_ih_decode_iv()
266 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);  in cik_ih_decode_iv()
267 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);  in cik_ih_decode_iv()
269 	entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY;  in cik_ih_decode_iv()
270 	entry->src_id = dw[0] & 0xff;  in cik_ih_decode_iv()
271 	entry->src_data[0] = dw[1] & 0xfffffff;  in cik_ih_decode_iv()
272 	entry->ring_id = dw[2] & 0xff;  in cik_ih_decode_iv()
273 	entry->vmid = (dw[2] >> 8) & 0xff;  in cik_ih_decode_iv()
274 	entry->pasid = (dw[2] >> 16) & 0xffff;  in cik_ih_decode_iv()
277 	ih->rptr += 16;  in cik_ih_decode_iv()
281  * cik_ih_set_rptr - set the IH ring buffer rptr
284  * @ih: IH ring buffer to set wptr
286  * Set the IH ring buffer rptr.
291 	WREG32(mmIH_RB_RPTR, ih->rptr);  in cik_ih_set_rptr()
296 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_early_init()
311 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_sw_init()
313 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false);  in cik_ih_sw_init()
317 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);  in cik_ih_sw_init()
328 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_sw_fini()
338 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_hw_init()
345 	cik_ih_irq_disable(ip_block->adev);  in cik_ih_hw_fini()
362 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_is_idle()
375 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_wait_for_idle()
377 	for (i = 0; i < adev->usec_timeout; i++) {  in cik_ih_wait_for_idle()
384 	return -ETIMEDOUT;  in cik_ih_wait_for_idle()
389 	struct amdgpu_device *adev = ip_block->adev;  in cik_ih_soft_reset()
400 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in cik_ih_soft_reset()
453 	adev->irq.ih_funcs = &cik_ih_funcs;  in cik_ih_set_interrupt_funcs()