Lines Matching refs:xcp_id
33 #define XCP_INST_MASK(num_inst, xcp_id) \
34 (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0)
73 int xcp_id;
77 ring->xcp_id = AMDGPU_XCP_NO_PARTITION;
79 adev->gfx.enforce_isolation[0].xcp_id = ring->xcp_id;
104 for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) {
105 if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) {
106 ring->xcp_id = xcp_id;
107 dev_dbg(adev->dev, "ring:%s xcp_id :%u", ring->name,
108 ring->xcp_id);
110 adev->gfx.enforce_isolation[xcp_id].xcp_id = xcp_id;
151 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);
159 aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);
193 if (fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION) {
196 fpriv->xcp_id = 0;
202 fpriv->xcp_id = i;
207 sel_xcp_id = fpriv->xcp_id;
210 *num_scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].num_scheds;
211 *scheds = adev->xcp_mgr->xcp[fpriv->xcp_id].gpu_sched[hw_ip][hw_prio].sched;
393 static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
426 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id);
430 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id);
434 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id);
439 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn);
769 static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
776 return __aqua_vanjaram_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip);