939 	pcie_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_pcie_state()
940 	pcie_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_pcie_state()
941 	pcie_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_pcie_state()
942 	pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE;  in aqua_vanjaram_read_pcie_state()
943 	pcie_reg_state->common_header.num_instances = 1;  in aqua_vanjaram_read_pcie_state()
945 	return pcie_reg_state->common_header.structure_size;  in aqua_vanjaram_read_pcie_state()
1023 	xgmi_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_xgmi_state()
1024 	xgmi_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_xgmi_state()
1025 	xgmi_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_xgmi_state()
1026 	xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI;  in aqua_vanjaram_read_xgmi_state()
1027 	xgmi_reg_state->common_header.num_instances = max_xgmi_instances;  in aqua_vanjaram_read_xgmi_state()
1029 	return xgmi_reg_state->common_header.structure_size;  in aqua_vanjaram_read_xgmi_state()
1096 	wafl_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_wafl_state()
1097 	wafl_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_wafl_state()
1098 	wafl_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_wafl_state()
1099 	wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL;  in aqua_vanjaram_read_wafl_state()
1100 	wafl_reg_state->common_header.num_instances = max_wafl_instances;  in aqua_vanjaram_read_wafl_state()
1102 	return wafl_reg_state->common_header.structure_size;  in aqua_vanjaram_read_wafl_state()
1215 	usr_reg_state->common_header.structure_size = szbuf;  in aqua_vanjaram_read_usr_state()
1216 	usr_reg_state->common_header.format_revision = 1;  in aqua_vanjaram_read_usr_state()
1217 	usr_reg_state->common_header.content_revision = 0;  in aqua_vanjaram_read_usr_state()
1218 	usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR;  in aqua_vanjaram_read_usr_state()
1219 	usr_reg_state->common_header.num_instances = max_usr_instances;  in aqua_vanjaram_read_usr_state()
1221 	return usr_reg_state->common_header.structure_size;  in aqua_vanjaram_read_usr_state()