Lines Matching +full:reset +full:- +full:bps
45 vf2pf_info->ucode_info[ucode].id = ucode; \
46 vf2pf_info->ucode_info[ucode].version = ver; \
74 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
75 adev->asic_type != CHIP_ARCTURUS && in amdgpu_virt_init_setting()
76 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { in amdgpu_virt_init_setting()
77 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
78 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
79 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
81 ddev->driver_features &= ~DRIVER_ATOMIC; in amdgpu_virt_init_setting()
82 adev->cg_flags = 0; in amdgpu_virt_init_setting()
83 adev->pg_flags = 0; in amdgpu_virt_init_setting()
86 if (amdgpu_num_kcq == -1) in amdgpu_virt_init_setting()
91 * amdgpu_virt_request_full_gpu() - request full gpu access
99 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_full_gpu()
102 if (virt->ops && virt->ops->req_full_gpu) { in amdgpu_virt_request_full_gpu()
103 r = virt->ops->req_full_gpu(adev, init); in amdgpu_virt_request_full_gpu()
105 adev->no_hw_access = true; in amdgpu_virt_request_full_gpu()
109 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_request_full_gpu()
116 * amdgpu_virt_release_full_gpu() - release full gpu access
124 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_release_full_gpu()
127 if (virt->ops && virt->ops->rel_full_gpu) { in amdgpu_virt_release_full_gpu()
128 r = virt->ops->rel_full_gpu(adev, init); in amdgpu_virt_release_full_gpu()
132 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_release_full_gpu()
138 * amdgpu_virt_reset_gpu() - reset gpu
140 * Send reset command to GPU hypervisor to reset GPU that VM is using
141 * Return: Zero if reset success, otherwise will return error.
145 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_reset_gpu()
148 if (virt->ops && virt->ops->reset_gpu) { in amdgpu_virt_reset_gpu()
149 r = virt->ops->reset_gpu(adev); in amdgpu_virt_reset_gpu()
153 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_reset_gpu()
161 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_init_data()
163 if (virt->ops && virt->ops->req_init_data) in amdgpu_virt_request_init_data()
164 virt->ops->req_init_data(adev); in amdgpu_virt_request_init_data()
166 if (adev->virt.req_init_data_ver > 0) in amdgpu_virt_request_init_data()
167 dev_info(adev->dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n", in amdgpu_virt_request_init_data()
168 adev->virt.req_init_data_ver); in amdgpu_virt_request_init_data()
170 dev_warn(adev->dev, "host doesn't support REQ_INIT_DATA handshake\n"); in amdgpu_virt_request_init_data()
174 * amdgpu_virt_ready_to_reset() - send ready to reset to host
176 * Send ready to reset message to GPU hypervisor to signal we have stopped GPU
181 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ready_to_reset()
183 if (virt->ops && virt->ops->reset_gpu) in amdgpu_virt_ready_to_reset()
184 virt->ops->ready_to_reset(adev); in amdgpu_virt_ready_to_reset()
188 * amdgpu_virt_wait_reset() - wait for reset gpu completed
190 * Wait for GPU reset completed.
191 * Return: Zero if reset success, otherwise will return error.
195 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_wait_reset()
197 if (!virt->ops || !virt->ops->wait_reset) in amdgpu_virt_wait_reset()
198 return -EINVAL; in amdgpu_virt_wait_reset()
200 return virt->ops->wait_reset(adev); in amdgpu_virt_wait_reset()
204 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table
213 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
219 &adev->virt.mm_table.bo, in amdgpu_virt_alloc_mm_table()
220 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
221 (void *)&adev->virt.mm_table.cpu_addr); in amdgpu_virt_alloc_mm_table()
223 dev_err(adev->dev, "failed to alloc mm table and error = %d.\n", r); in amdgpu_virt_alloc_mm_table()
227 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); in amdgpu_virt_alloc_mm_table()
228 dev_info(adev->dev, "MM table gpu addr = 0x%llx, cpu addr = %p.\n", in amdgpu_virt_alloc_mm_table()
229 adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
230 adev->virt.mm_table.cpu_addr); in amdgpu_virt_alloc_mm_table()
235 * amdgpu_virt_free_mm_table() - free mm table memory
241 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
244 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, in amdgpu_virt_free_mm_table()
245 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_free_mm_table()
246 (void *)&adev->virt.mm_table.cpu_addr); in amdgpu_virt_free_mm_table()
247 adev->virt.mm_table.gpu_addr = 0; in amdgpu_virt_free_mm_table()
251 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt
258 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_rcvd_ras_interrupt()
260 if (!virt->ops || !virt->ops->rcvd_ras_intr) in amdgpu_virt_rcvd_ras_interrupt()
263 return virt->ops->rcvd_ras_intr(adev); in amdgpu_virt_rcvd_ras_interrupt()
283 ret -= *(pos + i); in amd_sriov_msg_checksum()
292 * amdgpu_virt_ras_realloc_eh_data_space - alloc/realloc VF bad-page @data->bps and @data->bps_bo
294 * @data: VF RAS error-handler data
295 * @pages: minimum number of new slots to add beyond @data->capacity
297 * Return: 0 on success, %-ENOMEM on failure.
309 old_space = (unsigned int)data->capacity; in amdgpu_virt_ras_realloc_eh_data_space()
313 return -ENOMEM; in amdgpu_virt_ras_realloc_eh_data_space()
317 return -ENOMEM; in amdgpu_virt_ras_realloc_eh_data_space()
319 new_bps = kmalloc_objs(*data->bps, align_space); in amdgpu_virt_ras_realloc_eh_data_space()
320 new_bo = kzalloc_objs(*data->bps_bo, align_space); in amdgpu_virt_ras_realloc_eh_data_space()
324 dev_warn_ratelimited(adev->dev, in amdgpu_virt_ras_realloc_eh_data_space()
327 return -ENOMEM; in amdgpu_virt_ras_realloc_eh_data_space()
330 memcpy(new_bps, data->bps, data->count * sizeof(*data->bps)); in amdgpu_virt_ras_realloc_eh_data_space()
331 memcpy(new_bo, data->bps_bo, data->count * sizeof(*data->bps_bo)); in amdgpu_virt_ras_realloc_eh_data_space()
333 kfree(data->bps); in amdgpu_virt_ras_realloc_eh_data_space()
334 kfree(data->bps_bo); in amdgpu_virt_ras_realloc_eh_data_space()
335 data->bps = new_bps; in amdgpu_virt_ras_realloc_eh_data_space()
336 data->bps_bo = new_bo; in amdgpu_virt_ras_realloc_eh_data_space()
337 data->capacity = (int)align_space; in amdgpu_virt_ras_realloc_eh_data_space()
344 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_init_ras_err_handler_data()
345 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; in amdgpu_virt_init_ras_err_handler_data()
347 void *bps = NULL; in amdgpu_virt_init_ras_err_handler_data() local
354 bps = kmalloc_objs(*(*data)->bps, align_space); in amdgpu_virt_init_ras_err_handler_data()
355 if (!bps) in amdgpu_virt_init_ras_err_handler_data()
358 bps_bo = kzalloc_objs(*(*data)->bps_bo, align_space); in amdgpu_virt_init_ras_err_handler_data()
362 (*data)->bps = bps; in amdgpu_virt_init_ras_err_handler_data()
363 (*data)->bps_bo = bps_bo; in amdgpu_virt_init_ras_err_handler_data()
364 (*data)->capacity = align_space; in amdgpu_virt_init_ras_err_handler_data()
365 (*data)->count = 0; in amdgpu_virt_init_ras_err_handler_data()
366 (*data)->last_reserved = 0; in amdgpu_virt_init_ras_err_handler_data()
368 virt->ras_init_done = true; in amdgpu_virt_init_ras_err_handler_data()
373 kfree(bps); in amdgpu_virt_init_ras_err_handler_data()
377 return -ENOMEM; in amdgpu_virt_init_ras_err_handler_data()
382 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_release_bp()
383 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; in amdgpu_virt_ras_release_bp()
390 for (i = data->last_reserved - 1; i >= 0; i--) { in amdgpu_virt_ras_release_bp()
391 bo = data->bps_bo[i]; in amdgpu_virt_ras_release_bp()
394 data->bps_bo[i] = bo; in amdgpu_virt_ras_release_bp()
396 data->last_reserved = i; in amdgpu_virt_ras_release_bp()
402 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_release_ras_err_handler_data()
403 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; in amdgpu_virt_release_ras_err_handler_data()
405 virt->ras_init_done = false; in amdgpu_virt_release_ras_err_handler_data()
412 kfree(data->bps); in amdgpu_virt_release_ras_err_handler_data()
413 kfree(data->bps_bo); in amdgpu_virt_release_ras_err_handler_data()
415 virt->virt_eh_data = NULL; in amdgpu_virt_release_ras_err_handler_data()
419 const struct eeprom_table_record *bps, int pages) in amdgpu_virt_ras_add_bps() argument
421 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_add_bps()
422 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; in amdgpu_virt_ras_add_bps()
428 if (pages > AMDGPU_VIRT_RAS_BAD_PAGE_TABLE_MAX_CAPACITY - data->count) { in amdgpu_virt_ras_add_bps()
429 dev_warn_ratelimited(adev->dev, in amdgpu_virt_ras_add_bps()
431 data->count, pages, in amdgpu_virt_ras_add_bps()
436 need = data->count + pages; in amdgpu_virt_ras_add_bps()
437 if (need > data->capacity && in amdgpu_virt_ras_add_bps()
438 amdgpu_virt_ras_realloc_eh_data_space(adev, data, need - data->capacity)) in amdgpu_virt_ras_add_bps()
441 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); in amdgpu_virt_ras_add_bps()
442 data->count += pages; in amdgpu_virt_ras_add_bps()
449 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_reserve_bps()
450 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; in amdgpu_virt_ras_reserve_bps()
451 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; in amdgpu_virt_ras_reserve_bps()
452 struct ttm_resource_manager *man = &mgr->manager; in amdgpu_virt_ras_reserve_bps()
460 for (i = data->last_reserved; i < data->count; i++) { in amdgpu_virt_ras_reserve_bps()
461 bp = data->bps[i].retired_page; in amdgpu_virt_ras_reserve_bps()
469 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, in amdgpu_virt_ras_reserve_bps()
472 data->bps_bo[i] = NULL; in amdgpu_virt_ras_reserve_bps()
477 dev_dbg(adev->dev, in amdgpu_virt_ras_reserve_bps()
480 data->bps_bo[i] = bo; in amdgpu_virt_ras_reserve_bps()
482 data->last_reserved = i + 1; in amdgpu_virt_ras_reserve_bps()
490 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_check_bad_page()
491 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; in amdgpu_virt_ras_check_bad_page()
497 for (i = 0; i < data->count; i++) in amdgpu_virt_ras_check_bad_page()
498 if (retired_page == data->bps[i].retired_page) in amdgpu_virt_ras_check_bad_page()
510 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; in amdgpu_virt_add_bad_page()
511 void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; in amdgpu_virt_add_bad_page()
537 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; in amdgpu_virt_read_pf2vf_data()
547 if (adev->virt.fw_reserve.p_pf2vf == NULL) in amdgpu_virt_read_pf2vf_data()
548 return -EINVAL; in amdgpu_virt_read_pf2vf_data()
550 if (pf2vf_info->size > 1024) { in amdgpu_virt_read_pf2vf_data()
551 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); in amdgpu_virt_read_pf2vf_data()
552 return -EINVAL; in amdgpu_virt_read_pf2vf_data()
555 switch (pf2vf_info->version) { in amdgpu_virt_read_pf2vf_data()
558 checksum = pf2vf_v1->checksum; in amdgpu_virt_read_pf2vf_data()
560 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, in amdgpu_virt_read_pf2vf_data()
561 adev->virt.fw_reserve.checksum_key, checksum); in amdgpu_virt_read_pf2vf_data()
563 dev_err(adev->dev, in amdgpu_virt_read_pf2vf_data()
566 return -EINVAL; in amdgpu_virt_read_pf2vf_data()
569 adev->virt.gim_feature = pf2vf_v1->feature_flags; in amdgpu_virt_read_pf2vf_data()
574 checksum = pf2vf->checksum; in amdgpu_virt_read_pf2vf_data()
576 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, in amdgpu_virt_read_pf2vf_data()
579 dev_err(adev->dev, in amdgpu_virt_read_pf2vf_data()
582 return -EINVAL; in amdgpu_virt_read_pf2vf_data()
585 adev->virt.vf2pf_update_interval_ms = in amdgpu_virt_read_pf2vf_data()
586 pf2vf->vf2pf_update_interval_ms; in amdgpu_virt_read_pf2vf_data()
587 adev->virt.gim_feature = pf2vf->feature_flags.all; in amdgpu_virt_read_pf2vf_data()
588 adev->virt.reg_access = pf2vf->reg_access_flags.all; in amdgpu_virt_read_pf2vf_data()
590 adev->virt.decode_max_dimension_pixels = 0; in amdgpu_virt_read_pf2vf_data()
591 adev->virt.decode_max_frame_pixels = 0; in amdgpu_virt_read_pf2vf_data()
592 adev->virt.encode_max_dimension_pixels = 0; in amdgpu_virt_read_pf2vf_data()
593 adev->virt.encode_max_frame_pixels = 0; in amdgpu_virt_read_pf2vf_data()
594 adev->virt.is_mm_bw_enabled = false; in amdgpu_virt_read_pf2vf_data()
596 tmp = pf2vf->mm_bw_management[i].decode_max_dimension_pixels; in amdgpu_virt_read_pf2vf_data()
597 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); in amdgpu_virt_read_pf2vf_data()
599 tmp = pf2vf->mm_bw_management[i].decode_max_frame_pixels; in amdgpu_virt_read_pf2vf_data()
600 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); in amdgpu_virt_read_pf2vf_data()
602 tmp = pf2vf->mm_bw_management[i].encode_max_dimension_pixels; in amdgpu_virt_read_pf2vf_data()
603 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); in amdgpu_virt_read_pf2vf_data()
605 tmp = pf2vf->mm_bw_management[i].encode_max_frame_pixels; in amdgpu_virt_read_pf2vf_data()
606 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); in amdgpu_virt_read_pf2vf_data()
608 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) in amdgpu_virt_read_pf2vf_data()
609 adev->virt.is_mm_bw_enabled = true; in amdgpu_virt_read_pf2vf_data()
611 adev->unique_id = pf2vf->uuid; in amdgpu_virt_read_pf2vf_data()
613 adev->unitid = 0; in amdgpu_virt_read_pf2vf_data()
615 adev->unitid = pf2vf->unitid; in amdgpu_virt_read_pf2vf_data()
617 adev->virt.ras_en_caps.all = pf2vf->ras_en_caps.all; in amdgpu_virt_read_pf2vf_data()
618 adev->virt.ras_telemetry_en_caps.all = in amdgpu_virt_read_pf2vf_data()
619 pf2vf->ras_telemetry_en_caps.all; in amdgpu_virt_read_pf2vf_data()
622 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); in amdgpu_virt_read_pf2vf_data()
623 return -EINVAL; in amdgpu_virt_read_pf2vf_data()
627 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) in amdgpu_virt_read_pf2vf_data()
628 adev->virt.vf2pf_update_interval_ms = 2000; in amdgpu_virt_read_pf2vf_data()
636 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; in amdgpu_virt_populate_vf2pf_ucode_info()
638 if (adev->virt.fw_reserve.p_vf2pf == NULL) in amdgpu_virt_populate_vf2pf_ucode_info()
641 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
642 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
643 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
644 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
645 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
646 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
647 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
648 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
649 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
650 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
651 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
652 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
653 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
655 adev->psp.asd_context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
657 adev->psp.ras_context.context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
659 adev->psp.xgmi_context.context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
660 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
661 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
662 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
663 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
664 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
671 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; in amdgpu_virt_write_vf2pf_data()
673 if (adev->virt.fw_reserve.p_vf2pf == NULL) in amdgpu_virt_write_vf2pf_data()
674 return -EINVAL; in amdgpu_virt_write_vf2pf_data()
678 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); in amdgpu_virt_write_vf2pf_data()
679 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; in amdgpu_virt_write_vf2pf_data()
682 if (THIS_MODULE->version != NULL) in amdgpu_virt_write_vf2pf_data()
683 strscpy(vf2pf_info->driver_version, THIS_MODULE->version); in amdgpu_virt_write_vf2pf_data()
686 strscpy(vf2pf_info->driver_version, "N/A"); in amdgpu_virt_write_vf2pf_data()
688 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all in amdgpu_virt_write_vf2pf_data()
689 vf2pf_info->driver_cert = 0; in amdgpu_virt_write_vf2pf_data()
690 vf2pf_info->os_info.all = 0; in amdgpu_virt_write_vf2pf_data()
692 vf2pf_info->fb_usage = ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? in amdgpu_virt_write_vf2pf_data()
693 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20 : 0; in amdgpu_virt_write_vf2pf_data()
694 vf2pf_info->fb_vis_usage = in amdgpu_virt_write_vf2pf_data()
695 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; in amdgpu_virt_write_vf2pf_data()
696 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; in amdgpu_virt_write_vf2pf_data()
697 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; in amdgpu_virt_write_vf2pf_data()
702 vf2pf_info->gfx_usage = 0; in amdgpu_virt_write_vf2pf_data()
703 vf2pf_info->compute_usage = 0; in amdgpu_virt_write_vf2pf_data()
704 vf2pf_info->encode_usage = 0; in amdgpu_virt_write_vf2pf_data()
705 vf2pf_info->decode_usage = 0; in amdgpu_virt_write_vf2pf_data()
707 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; in amdgpu_virt_write_vf2pf_data()
709 vf2pf_info->mes_info_addr = in amdgpu_virt_write_vf2pf_data()
710 (uint64_t)(adev->mes.resource_1_gpu_addr[0] + AMDGPU_GPU_PAGE_SIZE); in amdgpu_virt_write_vf2pf_data()
711 vf2pf_info->mes_info_size = in amdgpu_virt_write_vf2pf_data()
712 adev->mes.resource_1[0]->tbo.base.size - AMDGPU_GPU_PAGE_SIZE; in amdgpu_virt_write_vf2pf_data()
714 vf2pf_info->checksum = in amdgpu_virt_write_vf2pf_data()
728 adev->virt.vf2pf_update_retry_cnt++; in amdgpu_virt_update_vf2pf_work_item()
731 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && in amdgpu_virt_update_vf2pf_work_item()
735 if (amdgpu_reset_domain_schedule(adev->reset_domain, in amdgpu_virt_update_vf2pf_work_item()
736 &adev->kfd.reset_work)) in amdgpu_virt_update_vf2pf_work_item()
739 dev_err(adev->dev, "Failed to queue work! at %s", __func__); in amdgpu_virt_update_vf2pf_work_item()
745 adev->virt.vf2pf_update_retry_cnt = 0; in amdgpu_virt_update_vf2pf_work_item()
749 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); in amdgpu_virt_update_vf2pf_work_item()
755 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset; in amdgpu_virt_read_exchange_data_from_mem()
757 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10; in amdgpu_virt_read_exchange_data_from_mem()
760 dev_info(adev->dev, in amdgpu_virt_read_exchange_data_from_mem()
765 dev_err(adev->dev, "Data exchange data not aligned to 4 bytes\n"); in amdgpu_virt_read_exchange_data_from_mem()
766 return -EINVAL; in amdgpu_virt_read_exchange_data_from_mem()
778 if (adev->virt.vf2pf_update_interval_ms != 0) { in amdgpu_virt_fini_data_exchange()
779 dev_info(adev->dev, "clean up the vf2pf work item\n"); in amdgpu_virt_fini_data_exchange()
780 cancel_delayed_work_sync(&adev->virt.vf2pf_work); in amdgpu_virt_fini_data_exchange()
781 adev->virt.vf2pf_update_interval_ms = 0; in amdgpu_virt_fini_data_exchange()
788 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; in amdgpu_virt_init_data_exchange()
789 void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; in amdgpu_virt_init_data_exchange()
791 adev->virt.fw_reserve.p_pf2vf = NULL; in amdgpu_virt_init_data_exchange()
792 adev->virt.fw_reserve.p_vf2pf = NULL; in amdgpu_virt_init_data_exchange()
793 adev->virt.vf2pf_update_interval_ms = 0; in amdgpu_virt_init_data_exchange()
794 adev->virt.vf2pf_update_retry_cnt = 0; in amdgpu_virt_init_data_exchange()
797 dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!"); in amdgpu_virt_init_data_exchange()
799 /* go through this logic in ip_init and reset to init workqueue*/ in amdgpu_virt_init_data_exchange()
802 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); in amdgpu_virt_init_data_exchange()
803 …schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_… in amdgpu_virt_init_data_exchange()
804 } else if (adev->bios != NULL) { in amdgpu_virt_init_data_exchange()
806 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { in amdgpu_virt_init_data_exchange()
808 kzalloc(adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb << 10, in amdgpu_virt_init_data_exchange()
811 dev_err(adev->dev, "Failed to allocate memory for pfvf_data\n"); in amdgpu_virt_init_data_exchange()
818 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_init_data_exchange()
826 adev->virt.fw_reserve.p_pf2vf = NULL; in amdgpu_virt_init_data_exchange()
828 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_init_data_exchange()
830 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); in amdgpu_virt_init_data_exchange()
843 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; in amdgpu_virt_exchange_data()
844 void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; in amdgpu_virt_exchange_data()
848 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { in amdgpu_virt_exchange_data()
849 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_exchange_data()
852 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset); in amdgpu_virt_exchange_data()
853 adev->virt.fw_reserve.p_vf2pf = in amdgpu_virt_exchange_data()
856 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset + in amdgpu_virt_exchange_data()
858 adev->virt.fw_reserve.ras_telemetry = in amdgpu_virt_exchange_data()
860 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset); in amdgpu_virt_exchange_data()
862 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_exchange_data()
865 adev->virt.fw_reserve.p_vf2pf = in amdgpu_virt_exchange_data()
868 adev->virt.fw_reserve.ras_telemetry = in amdgpu_virt_exchange_data()
872 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_exchange_data()
875 adev->virt.fw_reserve.p_vf2pf = in amdgpu_virt_exchange_data()
878 adev->virt.fw_reserve.ras_telemetry = in amdgpu_virt_exchange_data()
886 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { in amdgpu_virt_exchange_data()
887 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; in amdgpu_virt_exchange_data()
889 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | in amdgpu_virt_exchange_data()
890 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); in amdgpu_virt_exchange_data()
891 bp_block_size = pf2vf_v2->bp_block_size; in amdgpu_virt_exchange_data()
893 if (bp_block_size && !adev->virt.ras_init_done) in amdgpu_virt_exchange_data()
896 if (adev->virt.ras_init_done) in amdgpu_virt_exchange_data()
906 switch (adev->asic_type) { in amdgpu_virt_init_detect_asic()
927 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; in amdgpu_virt_init_detect_asic()
930 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; in amdgpu_virt_init_detect_asic()
935 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in amdgpu_virt_init_detect_asic()
949 switch (adev->asic_type) { in amdgpu_virt_init_req_data()
978 dev_err(adev->dev, "Unknown asic type: %d!\n", adev->asic_type); in amdgpu_virt_init_req_data()
988 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
989 ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
990 ratelimit_state_init(&adev->virt.ras.ras_chk_criti_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
992 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, in amdgpu_virt_init_ras()
994 ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, in amdgpu_virt_init_ras()
996 ratelimit_set_flags(&adev->virt.ras.ras_chk_criti_rs, in amdgpu_virt_init_ras()
999 mutex_init(&adev->virt.ras.ras_telemetry_mutex); in amdgpu_virt_init_ras()
1000 mutex_init(&adev->virt.access_req_mutex); in amdgpu_virt_init_ras()
1002 adev->virt.ras.cper_rptr = 0; in amdgpu_virt_init_ras()
1015 return 0xffffffff - sum; in amdgpu_virt_crit_region_calc_checksum()
1021 u64 init_hdr_offset = adev->virt.init_data_header.offset; in amdgpu_virt_init_critical_region()
1022 u64 init_hdr_size = (u64)adev->virt.init_data_header.size_kb << 10; /* KB → bytes */ in amdgpu_virt_init_critical_region()
1029 if (adev->virt.req_init_data_ver != GPU_CRIT_REGION_V2) in amdgpu_virt_init_critical_region()
1034 return -EINVAL; in amdgpu_virt_init_critical_region()
1038 dev_err(adev->dev, "init_data_header exceeds VRAM size, exiting\n"); in amdgpu_virt_init_critical_region()
1039 return -EINVAL; in amdgpu_virt_init_critical_region()
1045 return -ENOMEM; in amdgpu_virt_init_critical_region()
1051 if (strncmp(init_data_hdr->signature, in amdgpu_virt_init_critical_region()
1054 dev_err(adev->dev, "Invalid init data signature: %.4s\n", in amdgpu_virt_init_critical_region()
1055 init_data_hdr->signature); in amdgpu_virt_init_critical_region()
1056 r = -EINVAL; in amdgpu_virt_init_critical_region()
1061 (uint8_t *)&init_data_hdr->initdata_offset, in amdgpu_virt_init_critical_region()
1064 if (checksum != init_data_hdr->checksum) { in amdgpu_virt_init_critical_region()
1065 dev_err(adev->dev, "Found unmatching checksum from calculation 0x%x and init_data 0x%x\n", in amdgpu_virt_init_critical_region()
1066 checksum, init_data_hdr->checksum); in amdgpu_virt_init_critical_region()
1067 r = -EINVAL; in amdgpu_virt_init_critical_region()
1071 memset(&adev->virt.crit_regn, 0, sizeof(adev->virt.crit_regn)); in amdgpu_virt_init_critical_region()
1072 memset(adev->virt.crit_regn_tbl, 0, sizeof(adev->virt.crit_regn_tbl)); in amdgpu_virt_init_critical_region()
1074 adev->virt.crit_regn.offset = init_data_hdr->initdata_offset; in amdgpu_virt_init_critical_region()
1075 adev->virt.crit_regn.size_kb = init_data_hdr->initdata_size_in_kb; in amdgpu_virt_init_critical_region()
1079 if (!init_data_hdr->ip_discovery_size_in_kb || in amdgpu_virt_init_critical_region()
1080 init_data_hdr->ip_discovery_size_in_kb > DISCOVERY_TMR_SIZE) { in amdgpu_virt_init_critical_region()
1081 dev_err(adev->dev, "Invalid %s size: 0x%x\n", in amdgpu_virt_init_critical_region()
1083 init_data_hdr->ip_discovery_size_in_kb); in amdgpu_virt_init_critical_region()
1084 r = -EINVAL; in amdgpu_virt_init_critical_region()
1088 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset = in amdgpu_virt_init_critical_region()
1089 init_data_hdr->ip_discovery_offset; in amdgpu_virt_init_critical_region()
1090 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb = in amdgpu_virt_init_critical_region()
1091 init_data_hdr->ip_discovery_size_in_kb; in amdgpu_virt_init_critical_region()
1095 if (!init_data_hdr->vbios_img_size_in_kb) { in amdgpu_virt_init_critical_region()
1096 dev_err(adev->dev, "Invalid %s size: 0x%x\n", in amdgpu_virt_init_critical_region()
1098 init_data_hdr->vbios_img_size_in_kb); in amdgpu_virt_init_critical_region()
1099 r = -EINVAL; in amdgpu_virt_init_critical_region()
1103 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].offset = in amdgpu_virt_init_critical_region()
1104 init_data_hdr->vbios_img_offset; in amdgpu_virt_init_critical_region()
1105 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_VBIOS_IMG_TABLE_ID].size_kb = in amdgpu_virt_init_critical_region()
1106 init_data_hdr->vbios_img_size_in_kb; in amdgpu_virt_init_critical_region()
1110 if (!init_data_hdr->ras_tele_info_size_in_kb) { in amdgpu_virt_init_critical_region()
1111 dev_err(adev->dev, "Invalid %s size: 0x%x\n", in amdgpu_virt_init_critical_region()
1113 init_data_hdr->ras_tele_info_size_in_kb); in amdgpu_virt_init_critical_region()
1114 r = -EINVAL; in amdgpu_virt_init_critical_region()
1118 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].offset = in amdgpu_virt_init_critical_region()
1119 init_data_hdr->ras_tele_info_offset; in amdgpu_virt_init_critical_region()
1120 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_RAS_TELEMETRY_TABLE_ID].size_kb = in amdgpu_virt_init_critical_region()
1121 init_data_hdr->ras_tele_info_size_in_kb; in amdgpu_virt_init_critical_region()
1125 if (!init_data_hdr->dataexchange_size_in_kb) { in amdgpu_virt_init_critical_region()
1126 dev_err(adev->dev, "Invalid %s size: 0x%x\n", in amdgpu_virt_init_critical_region()
1128 init_data_hdr->dataexchange_size_in_kb); in amdgpu_virt_init_critical_region()
1129 r = -EINVAL; in amdgpu_virt_init_critical_region()
1133 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].offset = in amdgpu_virt_init_critical_region()
1134 init_data_hdr->dataexchange_offset; in amdgpu_virt_init_critical_region()
1135 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_DATAEXCHANGE_TABLE_ID].size_kb = in amdgpu_virt_init_critical_region()
1136 init_data_hdr->dataexchange_size_in_kb; in amdgpu_virt_init_critical_region()
1140 if (!init_data_hdr->bad_page_size_in_kb) { in amdgpu_virt_init_critical_region()
1141 dev_err(adev->dev, "Invalid %s size: 0x%x\n", in amdgpu_virt_init_critical_region()
1143 init_data_hdr->bad_page_size_in_kb); in amdgpu_virt_init_critical_region()
1144 r = -EINVAL; in amdgpu_virt_init_critical_region()
1148 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].offset = in amdgpu_virt_init_critical_region()
1149 init_data_hdr->bad_page_info_offset; in amdgpu_virt_init_critical_region()
1150 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_BAD_PAGE_INFO_TABLE_ID].size_kb = in amdgpu_virt_init_critical_region()
1151 init_data_hdr->bad_page_size_in_kb; in amdgpu_virt_init_critical_region()
1155 if (adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb > DISCOVERY_TMR_SIZE) { in amdgpu_virt_init_critical_region()
1156 dev_err(adev->dev, "Invalid IP discovery size: 0x%x\n", in amdgpu_virt_init_critical_region()
1157 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb); in amdgpu_virt_init_critical_region()
1158 r = -EINVAL; in amdgpu_virt_init_critical_region()
1164 adev->virt.crit_regn.offset, in amdgpu_virt_init_critical_region()
1165 adev->virt.crit_regn.size_kb << 10, true); in amdgpu_virt_init_critical_region()
1166 dev_info(adev->dev, in amdgpu_virt_init_critical_region()
1168 init_data_hdr->version, in amdgpu_virt_init_critical_region()
1169 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset, in amdgpu_virt_init_critical_region()
1170 adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].size >> 10); in amdgpu_virt_init_critical_region()
1172 adev->virt.is_dynamic_crit_regn_enabled = true; in amdgpu_virt_init_critical_region()
1189 return -EINVAL; in amdgpu_virt_get_dynamic_data_info()
1191 data_offset = adev->virt.crit_regn_tbl[data_table_id].offset; in amdgpu_virt_get_dynamic_data_info()
1192 data_size = adev->virt.crit_regn_tbl[data_table_id].size_kb << 10; in amdgpu_virt_get_dynamic_data_info()
1196 return -EINVAL; in amdgpu_virt_get_dynamic_data_info()
1203 dev_dbg(adev->dev, in amdgpu_virt_get_dynamic_data_info()
1238 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_enable_access_debugfs()
1240 return -EPERM; in amdgpu_virt_enable_access_debugfs()
1248 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_disable_access_debugfs()
1277 /* force set to GFXOFF state after reset, in amdgpu_virt_post_reset()
1280 adev->gfx.is_poweron = false; in amdgpu_virt_post_reset()
1283 adev->mes.ring[0].sched.ready = false; in amdgpu_virt_post_reset()
1358 if (!adev->virt.is_mm_bw_enabled) in amdgpu_virt_update_sriov_video_codec()
1363 encode[i].max_width = adev->virt.encode_max_dimension_pixels; in amdgpu_virt_update_sriov_video_codec()
1364 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; in amdgpu_virt_update_sriov_video_codec()
1374 decode[i].max_width = adev->virt.decode_max_dimension_pixels; in amdgpu_virt_update_sriov_video_codec()
1375 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; in amdgpu_virt_update_sriov_video_codec()
1439 if (!adev->gfx.rlc.rlcg_reg_access_supported) { in amdgpu_virt_rlcg_vfi_reg_rw()
1440 dev_err(adev->dev, "VFi interface is not available\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1444 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_vfi_reg_rw()
1445 dev_err(adev->dev, "VFi invalid XCC, xcc_id=0x%x\n", xcc_id); in amdgpu_virt_rlcg_vfi_reg_rw()
1452 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_vfi_reg_rw()
1453 vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd; in amdgpu_virt_rlcg_vfi_reg_rw()
1454 vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat; in amdgpu_virt_rlcg_vfi_reg_rw()
1455 vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr; in amdgpu_virt_rlcg_vfi_reg_rw()
1456 vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data; in amdgpu_virt_rlcg_vfi_reg_rw()
1457 vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl; in amdgpu_virt_rlcg_vfi_reg_rw()
1458 vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx; in amdgpu_virt_rlcg_vfi_reg_rw()
1459 grbm_cntl_data = reg_access_ctrl->vfi_grbm_cntl_data; in amdgpu_virt_rlcg_vfi_reg_rw()
1460 grbm_idx_data = reg_access_ctrl->vfi_grbm_idx_data; in amdgpu_virt_rlcg_vfi_reg_rw()
1467 if (addr == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_vfi_reg_rw()
1468 reg_access_ctrl->vfi_grbm_cntl_data = data; in amdgpu_virt_rlcg_vfi_reg_rw()
1470 } else if (addr == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_vfi_reg_rw()
1471 reg_access_ctrl->vfi_grbm_idx_data = data; in amdgpu_virt_rlcg_vfi_reg_rw()
1480 if (addr == reg_access_ctrl->grbm_cntl) in amdgpu_virt_rlcg_vfi_reg_rw()
1482 else if (addr == reg_access_ctrl->grbm_idx) in amdgpu_virt_rlcg_vfi_reg_rw()
1486 dev_err(adev->dev, "VFi invalid access, flag=0x%x\n", flag); in amdgpu_virt_rlcg_vfi_reg_rw()
1490 spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); in amdgpu_virt_rlcg_vfi_reg_rw()
1514 dev_err(adev->dev, "VFi access timeout\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1517 dev_err(adev->dev, "VFi invalid command\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1520 dev_err(adev->dev, "VFi invalid address\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1523 dev_err(adev->dev, "VFi unknown error\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1526 dev_err(adev->dev, "VFi unknown status code\n"); in amdgpu_virt_rlcg_vfi_reg_rw()
1530 spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); in amdgpu_virt_rlcg_vfi_reg_rw()
1533 …dev_err(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd… in amdgpu_virt_rlcg_vfi_reg_rw()
1537 …dev_dbg(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd… in amdgpu_virt_rlcg_vfi_reg_rw()
1560 if (!adev->gfx.rlc.rlcg_reg_access_supported) { in amdgpu_virt_rlcg_reg_rw()
1561 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1566 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
1567 dev_err(adev->dev, "invalid xcc\n"); in amdgpu_virt_rlcg_reg_rw()
1574 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1575 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()
1576 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()
1577 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
1578 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()
1580 spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); in amdgpu_virt_rlcg_reg_rw()
1582 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw()
1583 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw()
1585 if (offset == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_reg_rw()
1589 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in amdgpu_virt_rlcg_reg_rw()
1590 } else if (offset == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_reg_rw()
1594 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in amdgpu_virt_rlcg_reg_rw()
1604 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw()
1618 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1621 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1624 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1627 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1631 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1639 spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); in amdgpu_virt_rlcg_reg_rw()
1701 if (adev->virt.ras_en_caps.bits.block_umc) in amdgpu_virt_get_ras_capability()
1702 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC); in amdgpu_virt_get_ras_capability()
1703 if (adev->virt.ras_en_caps.bits.block_sdma) in amdgpu_virt_get_ras_capability()
1704 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA); in amdgpu_virt_get_ras_capability()
1705 if (adev->virt.ras_en_caps.bits.block_gfx) in amdgpu_virt_get_ras_capability()
1706 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX); in amdgpu_virt_get_ras_capability()
1707 if (adev->virt.ras_en_caps.bits.block_mmhub) in amdgpu_virt_get_ras_capability()
1708 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB); in amdgpu_virt_get_ras_capability()
1709 if (adev->virt.ras_en_caps.bits.block_athub) in amdgpu_virt_get_ras_capability()
1710 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB); in amdgpu_virt_get_ras_capability()
1711 if (adev->virt.ras_en_caps.bits.block_pcie_bif) in amdgpu_virt_get_ras_capability()
1712 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF); in amdgpu_virt_get_ras_capability()
1713 if (adev->virt.ras_en_caps.bits.block_hdp) in amdgpu_virt_get_ras_capability()
1714 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP); in amdgpu_virt_get_ras_capability()
1715 if (adev->virt.ras_en_caps.bits.block_xgmi_wafl) in amdgpu_virt_get_ras_capability()
1716 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL); in amdgpu_virt_get_ras_capability()
1717 if (adev->virt.ras_en_caps.bits.block_df) in amdgpu_virt_get_ras_capability()
1718 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF); in amdgpu_virt_get_ras_capability()
1719 if (adev->virt.ras_en_caps.bits.block_smn) in amdgpu_virt_get_ras_capability()
1720 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN); in amdgpu_virt_get_ras_capability()
1721 if (adev->virt.ras_en_caps.bits.block_sem) in amdgpu_virt_get_ras_capability()
1722 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM); in amdgpu_virt_get_ras_capability()
1723 if (adev->virt.ras_en_caps.bits.block_mp0) in amdgpu_virt_get_ras_capability()
1724 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0); in amdgpu_virt_get_ras_capability()
1725 if (adev->virt.ras_en_caps.bits.block_mp1) in amdgpu_virt_get_ras_capability()
1726 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1); in amdgpu_virt_get_ras_capability()
1727 if (adev->virt.ras_en_caps.bits.block_fuse) in amdgpu_virt_get_ras_capability()
1728 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE); in amdgpu_virt_get_ras_capability()
1729 if (adev->virt.ras_en_caps.bits.block_mca) in amdgpu_virt_get_ras_capability()
1730 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA); in amdgpu_virt_get_ras_capability()
1731 if (adev->virt.ras_en_caps.bits.block_vcn) in amdgpu_virt_get_ras_capability()
1732 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN); in amdgpu_virt_get_ras_capability()
1733 if (adev->virt.ras_en_caps.bits.block_jpeg) in amdgpu_virt_get_ras_capability()
1734 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG); in amdgpu_virt_get_ras_capability()
1735 if (adev->virt.ras_en_caps.bits.block_ih) in amdgpu_virt_get_ras_capability()
1736 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH); in amdgpu_virt_get_ras_capability()
1737 if (adev->virt.ras_en_caps.bits.block_mpio) in amdgpu_virt_get_ras_capability()
1738 adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO); in amdgpu_virt_get_ras_capability()
1740 if (adev->virt.ras_en_caps.bits.poison_propogation_mode) in amdgpu_virt_get_ras_capability()
1741 con->poison_supported = true; /* Poison is handled by host */ in amdgpu_virt_get_ras_capability()
1743 if (adev->virt.ras_en_caps.bits.uniras_supported) in amdgpu_virt_get_ras_capability()
1791 dev_warn(adev->dev, "Unsupported SRIOV RAS telemetry block 0x%x\n", in amdgpu_ras_block_to_sriov()
1803 checksum = host_telemetry->header.checksum; in amdgpu_virt_cache_host_error_counts()
1804 used_size = host_telemetry->header.used_size; in amdgpu_virt_cache_host_error_counts()
1809 tmp = kmemdup(&host_telemetry->body.error_count, used_size, GFP_KERNEL); in amdgpu_virt_cache_host_error_counts()
1811 return -ENOMEM; in amdgpu_virt_cache_host_error_counts()
1816 memcpy(&adev->virt.count_cache, tmp, in amdgpu_virt_cache_host_error_counts()
1817 min(used_size, sizeof(adev->virt.count_cache))); in amdgpu_virt_cache_host_error_counts()
1826 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_req_ras_err_count_internal()
1828 if (!virt->ops || !virt->ops->req_ras_err_count) in amdgpu_virt_req_ras_err_count_internal()
1829 return -EOPNOTSUPP; in amdgpu_virt_req_ras_err_count_internal()
1835 if (__ratelimit(&virt->ras.ras_error_cnt_rs) || force_update) { in amdgpu_virt_req_ras_err_count_internal()
1836 mutex_lock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_err_count_internal()
1837 if (!virt->ops->req_ras_err_count(adev)) in amdgpu_virt_req_ras_err_count_internal()
1839 virt->fw_reserve.ras_telemetry); in amdgpu_virt_req_ras_err_count_internal()
1840 mutex_unlock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_err_count_internal()
1856 return -EOPNOTSUPP; in amdgpu_virt_req_ras_err_count()
1858 /* Host Access may be lost during reset, just return last cached data. */ in amdgpu_virt_req_ras_err_count()
1859 if (down_read_trylock(&adev->reset_domain->sem)) { in amdgpu_virt_req_ras_err_count()
1861 up_read(&adev->reset_domain->sem); in amdgpu_virt_req_ras_err_count()
1864 err_data->ue_count = adev->virt.count_cache.block[sriov_block].ue_count; in amdgpu_virt_req_ras_err_count()
1865 err_data->ce_count = adev->virt.count_cache.block[sriov_block].ce_count; in amdgpu_virt_req_ras_err_count()
1866 err_data->de_count = adev->virt.count_cache.block[sriov_block].de_count; in amdgpu_virt_req_ras_err_count()
1878 struct amdgpu_ring *ring = &adev->cper.ring_buf; in amdgpu_virt_write_cpers_to_ring()
1883 checksum = host_telemetry->header.checksum; in amdgpu_virt_write_cpers_to_ring()
1884 used_size = host_telemetry->header.used_size; in amdgpu_virt_write_cpers_to_ring()
1888 return -EINVAL; in amdgpu_virt_write_cpers_to_ring()
1890 cper_dump = kmemdup(&host_telemetry->body.cper_dump, used_size, GFP_KERNEL); in amdgpu_virt_write_cpers_to_ring()
1892 return -ENOMEM; in amdgpu_virt_write_cpers_to_ring()
1895 ret = -EINVAL; in amdgpu_virt_write_cpers_to_ring()
1899 *more = cper_dump->more; in amdgpu_virt_write_cpers_to_ring()
1901 if (cper_dump->wptr < adev->virt.ras.cper_rptr) { in amdgpu_virt_write_cpers_to_ring()
1903 adev->dev, in amdgpu_virt_write_cpers_to_ring()
1905 adev->virt.ras.cper_rptr, cper_dump->wptr); in amdgpu_virt_write_cpers_to_ring()
1907 adev->virt.ras.cper_rptr = cper_dump->wptr; in amdgpu_virt_write_cpers_to_ring()
1911 entry = (struct cper_hdr *)&cper_dump->buf[0]; in amdgpu_virt_write_cpers_to_ring()
1912 remaining = (u64)used_size - offsetof(struct amd_sriov_ras_cper_dump, buf); in amdgpu_virt_write_cpers_to_ring()
1913 cnt = min_t(u64, cper_dump->count, CPER_MAX_ALLOWED_COUNT); in amdgpu_virt_write_cpers_to_ring()
1916 if (entry->record_length < sizeof(struct cper_hdr) || in amdgpu_virt_write_cpers_to_ring()
1917 entry->record_length > remaining) { in amdgpu_virt_write_cpers_to_ring()
1918 ret = -EINVAL; in amdgpu_virt_write_cpers_to_ring()
1922 amdgpu_cper_ring_write(ring, entry, entry->record_length); in amdgpu_virt_write_cpers_to_ring()
1923 remaining -= entry->record_length; in amdgpu_virt_write_cpers_to_ring()
1924 entry = (struct cper_hdr *)((char *)entry + entry->record_length); in amdgpu_virt_write_cpers_to_ring()
1927 if (cper_dump->overflow_count) in amdgpu_virt_write_cpers_to_ring()
1928 dev_warn(adev->dev, in amdgpu_virt_write_cpers_to_ring()
1930 cper_dump->overflow_count); in amdgpu_virt_write_cpers_to_ring()
1932 adev->virt.ras.cper_rptr = cper_dump->wptr; in amdgpu_virt_write_cpers_to_ring()
1941 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_req_ras_cper_dump_internal()
1945 if (!virt->ops || !virt->ops->req_ras_cper_dump) in amdgpu_virt_req_ras_cper_dump_internal()
1946 return -EOPNOTSUPP; in amdgpu_virt_req_ras_cper_dump_internal()
1949 if (!virt->ops->req_ras_cper_dump(adev, virt->ras.cper_rptr)) in amdgpu_virt_req_ras_cper_dump_internal()
1951 adev, virt->fw_reserve.ras_telemetry, &more); in amdgpu_virt_req_ras_cper_dump_internal()
1961 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_req_ras_cper_dump()
1965 return -EOPNOTSUPP; in amdgpu_virt_req_ras_cper_dump()
1967 if ((__ratelimit(&virt->ras.ras_cper_dump_rs) || force_update) && in amdgpu_virt_req_ras_cper_dump()
1968 down_read_trylock(&adev->reset_domain->sem)) { in amdgpu_virt_req_ras_cper_dump()
1969 mutex_lock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_cper_dump()
1971 mutex_unlock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_req_ras_cper_dump()
1972 up_read(&adev->reset_domain->sem); in amdgpu_virt_req_ras_cper_dump()
2005 * amdgpu_virt_request_bad_pages() - request bad pages
2011 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_bad_pages()
2013 if (virt->ops && virt->ops->req_bad_pages) in amdgpu_virt_request_bad_pages()
2014 virt->ops->req_bad_pages(adev); in amdgpu_virt_request_bad_pages()
2024 checksum = host_telemetry->header.checksum; in amdgpu_virt_cache_chk_criti_hit()
2025 used_size = host_telemetry->header.used_size; in amdgpu_virt_cache_chk_criti_hit()
2030 tmp = kmemdup(&host_telemetry->body.chk_criti, used_size, GFP_KERNEL); in amdgpu_virt_cache_chk_criti_hit()
2032 return -ENOMEM; in amdgpu_virt_cache_chk_criti_hit()
2038 *hit = tmp->hit ? true : false; in amdgpu_virt_cache_chk_criti_hit()
2048 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_check_vf_critical_region()
2049 int r = -EPERM; in amdgpu_virt_check_vf_critical_region()
2051 if (!virt->ops || !virt->ops->req_ras_chk_criti) in amdgpu_virt_check_vf_critical_region()
2052 return -EOPNOTSUPP; in amdgpu_virt_check_vf_critical_region()
2058 if (__ratelimit(&virt->ras.ras_chk_criti_rs)) { in amdgpu_virt_check_vf_critical_region()
2059 mutex_lock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_check_vf_critical_region()
2060 if (!virt->ops->req_ras_chk_criti(adev, addr)) in amdgpu_virt_check_vf_critical_region()
2062 adev, virt->fw_reserve.ras_telemetry, hit); in amdgpu_virt_check_vf_critical_region()
2063 mutex_unlock(&virt->ras.ras_telemetry_mutex); in amdgpu_virt_check_vf_critical_region()
2072 struct amdgpu_virt *virt = &adev->virt; in req_remote_ras_cmd()
2074 if (virt->ops && virt->ops->req_remote_ras_cmd) in req_remote_ras_cmd()
2075 return virt->ops->req_remote_ras_cmd(adev, param1, param2, param3); in req_remote_ras_cmd()
2076 return -ENOENT; in req_remote_ras_cmd()
2083 int ret = -EIO; in amdgpu_virt_send_remote_ras_cmd()
2085 if (down_read_trylock(&adev->reset_domain->sem)) { in amdgpu_virt_send_remote_ras_cmd()
2088 up_read(&adev->reset_domain->sem); in amdgpu_virt_send_remote_ras_cmd()
2100 return -EINVAL; in amdgpu_virt_ptl_request()
2103 !adev->virt.ops || !adev->virt.ops->req_ptl_update) in amdgpu_virt_ptl_request()
2104 return -EOPNOTSUPP; in amdgpu_virt_ptl_request()
2108 dev_warn(adev->dev, in amdgpu_virt_ptl_request()
2111 return -EINVAL; in amdgpu_virt_ptl_request()
2115 ret = adev->virt.ops->req_ptl_update(adev, req_code, *ptl_state, *fmt1, *fmt2); in amdgpu_virt_ptl_request()
2117 dev_warn(adev->dev, "VF PTL update request failed: %d\n", ret); in amdgpu_virt_ptl_request()
2122 *ptl_state = adev->virt.ptl_state; in amdgpu_virt_ptl_request()
2123 *fmt1 = adev->virt.ptl_pref_format1; in amdgpu_virt_ptl_request()
2124 *fmt2 = adev->virt.ptl_pref_format2; in amdgpu_virt_ptl_request()