Lines Matching refs:vcn
107 adev->vcn.inst[i].adev = adev;
108 adev->vcn.inst[i].inst = i;
111 if (i != 0 && adev->vcn.per_inst_fw) {
112 r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
116 amdgpu_ucode_release(&adev->vcn.inst[i].fw);
118 if (!adev->vcn.inst[0].fw) {
119 r = amdgpu_ucode_request(adev, &adev->vcn.inst[0].fw,
123 amdgpu_ucode_release(&adev->vcn.inst[0].fw);
127 adev->vcn.inst[i].fw = adev->vcn.inst[0].fw;
141 mutex_init(&adev->vcn.inst[i].vcn1_jpeg1_workaround);
142 mutex_init(&adev->vcn.inst[i].vcn_pg_lock);
143 mutex_init(&adev->vcn.inst[i].engine_reset_mutex);
144 atomic_set(&adev->vcn.inst[i].total_submission_cnt, 0);
145 INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
146 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
149 adev->vcn.inst[i].indirect_sram = true;
163 adev->vcn.inst[i].indirect_sram = false;
170 adev->vcn.inst[i].using_unified_queue =
173 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
174 adev->vcn.inst[i].fw_version = le32_to_cpu(hdr->ucode_version);
175 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
228 &adev->vcn.inst[i].vcpu_bo,
229 &adev->vcn.inst[i].gpu_addr,
230 &adev->vcn.inst[i].cpu_addr);
232 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
236 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
238 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
241 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
244 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
245 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
246 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
249 if (adev->vcn.inst[i].indirect_sram) {
253 &adev->vcn.inst[i].dpg_sram_bo,
254 &adev->vcn.inst[i].dpg_sram_gpu_addr,
255 &adev->vcn.inst[i].dpg_sram_cpu_addr);
269 if (adev->vcn.harvest_config & (1 << i))
273 &adev->vcn.inst[i].dpg_sram_bo,
274 &adev->vcn.inst[i].dpg_sram_gpu_addr,
275 (void **)&adev->vcn.inst[i].dpg_sram_cpu_addr);
277 kvfree(adev->vcn.inst[i].saved_bo);
279 amdgpu_bo_free_kernel(&adev->vcn.inst[i].vcpu_bo,
280 &adev->vcn.inst[i].gpu_addr,
281 (void **)&adev->vcn.inst[i].cpu_addr);
283 amdgpu_ring_fini(&adev->vcn.inst[i].ring_dec);
285 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)
286 amdgpu_ring_fini(&adev->vcn.inst[i].ring_enc[j]);
288 if (adev->vcn.per_inst_fw) {
289 amdgpu_ucode_release(&adev->vcn.inst[i].fw);
291 amdgpu_ucode_release(&adev->vcn.inst[0].fw);
292 adev->vcn.inst[i].fw = NULL;
295 if (adev->vcn.reg_list)
298 mutex_destroy(&adev->vcn.inst[i].vcn_pg_lock);
299 mutex_destroy(&adev->vcn.inst[i].vcn1_jpeg1_workaround);
305 int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
323 if (adev->vcn.harvest_config & (1 << i))
325 if (adev->vcn.inst[i].vcpu_bo == NULL)
328 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
329 ptr = adev->vcn.inst[i].cpu_addr;
331 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
332 if (!adev->vcn.inst[i].saved_bo)
336 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
347 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
360 if (adev->vcn.harvest_config & (1 << i))
377 if (adev->vcn.harvest_config & (1 << i))
379 if (adev->vcn.inst[i].vcpu_bo == NULL)
382 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
383 ptr = adev->vcn.inst[i].cpu_addr;
385 if (adev->vcn.inst[i].saved_bo != NULL) {
387 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
390 kvfree(adev->vcn.inst[i].saved_bo);
391 adev->vcn.inst[i].saved_bo = NULL;
396 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
400 memcpy_toio(adev->vcn.inst[i].cpu_addr,
401 adev->vcn.inst[i].fw->data + offset,
418 mutex_lock(&adev->vcn.workload_profile_mutex);
420 if (adev->vcn.workload_profile_active) {
421 mutex_unlock(&adev->vcn.workload_profile_mutex);
430 adev->vcn.workload_profile_active = true;
431 mutex_unlock(&adev->vcn.workload_profile_mutex);
439 mutex_lock(&adev->vcn.workload_profile_mutex);
440 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
441 if (adev->vcn.inst[i].cur_state != AMD_PG_STATE_GATE) {
456 adev->vcn.workload_profile_active = false;
459 mutex_unlock(&adev->vcn.workload_profile_mutex);
470 if (adev->vcn.harvest_config & (1 << i))
473 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j)
478 !adev->vcn.inst[i].using_unified_queue) {
487 adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state);
507 struct amdgpu_vcn_inst *vcn_inst = &adev->vcn.inst[ring->me];
550 !adev->vcn.inst[ring->me].using_unified_queue)
551 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
553 atomic_dec(&ring->adev->vcn.inst[ring->me].total_submission_cnt);
555 schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work,
570 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
574 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
578 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
639 ib->ptr[0] = PACKET0(adev->vcn.inst[ring->me].internal.data0, 0);
641 ib->ptr[2] = PACKET0(adev->vcn.inst[ring->me].internal.data1, 0);
643 ib->ptr[4] = PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0);
646 ib->ptr[i] = PACKET0(adev->vcn.inst[ring->me].internal.nop, 0);
809 if (adev->vcn.inst[ring->me].using_unified_queue)
822 if (adev->vcn.inst[ring->me].using_unified_queue) {
841 if (adev->vcn.inst[ring->me].using_unified_queue)
939 if (adev->vcn.inst[ring->me].using_unified_queue)
953 if (adev->vcn.inst[ring->me].using_unified_queue)
975 if (adev->vcn.inst[ring->me].using_unified_queue)
1006 if (adev->vcn.inst[ring->me].using_unified_queue)
1020 if (adev->vcn.inst[ring->me].using_unified_queue)
1042 if (adev->vcn.inst[ring->me].using_unified_queue)
1135 if (adev->vcn.harvest_config & (1 << i))
1144 hdr = (const struct common_firmware_header *)adev->vcn.inst[i].fw->data;
1152 adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
1159 * debugfs for mapping vcn firmware log buffer.
1165 struct amdgpu_vcn_inst *vcn;
1171 vcn = file_inode(f)->i_private;
1172 if (!vcn)
1175 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1178 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1230 struct amdgpu_vcn_inst *vcn)
1238 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1244 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1247 uint32_t *flag = vcn->fw_shared.cpu_addr;
1248 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1249 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1251 struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1252 + vcn->fw_shared.log_offset;
1271 struct ras_common_if *ras_if = adev->vcn.ras_if;
1302 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1303 if (adev->vcn.harvest_config & (1 << i) ||
1304 !adev->vcn.inst[i].ras_poison_irq.funcs)
1307 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1324 if (!adev->vcn.ras)
1327 ras = adev->vcn.ras;
1330 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1334 strcpy(ras->ras_block.ras_comm.name, "vcn");
1337 adev->vcn.ras_if = &ras->ras_block.ras_comm;
1352 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1353 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1354 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),
1370 return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset);
1380 if (adev->vcn.num_vcn_inst) {
1392 if (adev->vcn.num_vcn_inst)
1398 * debugfs to enable/disable vcn job submission to specific core or
1412 mask = (1ULL << adev->vcn.num_vcn_inst) - 1;
1415 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1416 ring = &adev->vcn.inst[i].ring_enc[0];
1436 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1437 ring = &adev->vcn.inst[i].ring_enc[0];
1457 if (adev->vcn.num_vcn_inst <= 1 || !adev->vcn.inst[0].using_unified_queue)
1479 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1480 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
1504 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me];
1507 if (adev->vcn.inst[ring->me].using_unified_queue)
1556 adev->vcn.ip_dump = kcalloc(adev->vcn.num_vcn_inst * count,
1558 if (!adev->vcn.ip_dump)
1560 adev->vcn.reg_list = reg;
1561 adev->vcn.reg_count = count;
1568 kfree(adev->vcn.ip_dump);
1569 adev->vcn.ip_dump = NULL;
1570 adev->vcn.reg_list = NULL;
1571 adev->vcn.reg_count = 0;
1581 if (!adev->vcn.ip_dump)
1584 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1585 if (adev->vcn.harvest_config & (1 << i))
1588 inst_off = i * adev->vcn.reg_count;
1590 adev->vcn.ip_dump[inst_off] =
1591 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[0], i));
1592 is_powered = (adev->vcn.ip_dump[inst_off] &
1597 for (j = 1; j < adev->vcn.reg_count; j++)
1598 adev->vcn.ip_dump[inst_off + j] =
1599 RREG32(SOC15_REG_ENTRY_OFFSET_INST(adev->vcn.reg_list[j], i));
1610 if (!adev->vcn.ip_dump)
1613 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1614 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1615 if (adev->vcn.harvest_config & (1 << i)) {
1620 inst_off = i * adev->vcn.reg_count;
1621 is_powered = (adev->vcn.ip_dump[inst_off] &
1627 for (j = 0; j < adev->vcn.reg_count; j++)
1628 drm_printf(p, "%-50s \t 0x%08x\n", adev->vcn.reg_list[j].reg_name,
1629 adev->vcn.ip_dump[inst_off + j]);