Lines Matching +full:hdr +full:- +full:engine
42 struct amdgpu_device *adev = ring->adev; in amdgpu_sdma_get_instance_from_ring()
45 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
46 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_instance_from_ring()
47 ring == &adev->sdma.instance[i].page) in amdgpu_sdma_get_instance_from_ring()
48 return &adev->sdma.instance[i]; in amdgpu_sdma_get_instance_from_ring()
55 struct amdgpu_device *adev = ring->adev; in amdgpu_sdma_get_index_from_ring()
58 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
59 if (ring == &adev->sdma.instance[i].ring || in amdgpu_sdma_get_index_from_ring()
60 ring == &adev->sdma.instance[i].page) { in amdgpu_sdma_get_index_from_ring()
66 return -EINVAL; in amdgpu_sdma_get_index_from_ring()
72 struct amdgpu_device *adev = ring->adev; in amdgpu_sdma_get_csa_mc_addr()
78 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp) in amdgpu_sdma_get_csa_mc_addr()
102 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_sdma_ras_late_init()
103 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_ras_late_init()
104 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, in amdgpu_sdma_ras_late_init()
122 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); in amdgpu_sdma_process_ras_data_cb()
136 struct ras_common_if *ras_if = adev->sdma.ras_if; in amdgpu_sdma_process_ecc_irq()
154 const struct sdma_firmware_header_v1_0 *hdr; in amdgpu_sdma_init_inst_ctx() local
159 sdma_inst->fw->data; in amdgpu_sdma_init_inst_ctx()
160 version_major = le16_to_cpu(header->header_version_major); in amdgpu_sdma_init_inst_ctx()
164 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; in amdgpu_sdma_init_inst_ctx()
165 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); in amdgpu_sdma_init_inst_ctx()
166 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); in amdgpu_sdma_init_inst_ctx()
169 hdr_v2 = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data; in amdgpu_sdma_init_inst_ctx()
170 sdma_inst->fw_version = le32_to_cpu(hdr_v2->header.ucode_version); in amdgpu_sdma_init_inst_ctx()
171 sdma_inst->feature_version = le32_to_cpu(hdr_v2->ucode_feature_version); in amdgpu_sdma_init_inst_ctx()
174 hdr_v3 = (const struct sdma_firmware_header_v3_0 *)sdma_inst->fw->data; in amdgpu_sdma_init_inst_ctx()
175 sdma_inst->fw_version = le32_to_cpu(hdr_v3->header.ucode_version); in amdgpu_sdma_init_inst_ctx()
176 sdma_inst->feature_version = le32_to_cpu(hdr_v3->ucode_feature_version); in amdgpu_sdma_init_inst_ctx()
179 return -EINVAL; in amdgpu_sdma_init_inst_ctx()
182 if (sdma_inst->feature_version >= 20) in amdgpu_sdma_init_inst_ctx()
183 sdma_inst->burst_nop = true; in amdgpu_sdma_init_inst_ctx()
193 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_destroy_inst_ctx()
194 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in amdgpu_sdma_destroy_inst_ctx()
199 memset((void *)adev->sdma.instance, 0, in amdgpu_sdma_destroy_inst_ctx()
216 err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw, in amdgpu_sdma_init_microcode()
220 err = amdgpu_ucode_request(adev, &adev->sdma.instance[instance].fw, in amdgpu_sdma_init_microcode()
227 adev->sdma.instance[instance].fw->data; in amdgpu_sdma_init_microcode()
228 version_major = le16_to_cpu(header->header_version_major); in amdgpu_sdma_init_microcode()
231 err = -EINVAL; in amdgpu_sdma_init_microcode()
235 err = amdgpu_sdma_init_inst_ctx(&adev->sdma.instance[instance]); in amdgpu_sdma_init_microcode()
240 for (i = 1; i < adev->sdma.num_instances; i++) in amdgpu_sdma_init_microcode()
241 memcpy((void *)&adev->sdma.instance[i], in amdgpu_sdma_init_microcode()
242 (void *)&adev->sdma.instance[0], in amdgpu_sdma_init_microcode()
247 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); in amdgpu_sdma_init_microcode()
249 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_sdma_init_microcode()
252 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_init_microcode()
264 adev->firmware.load_type == in amdgpu_sdma_init_microcode()
266 adev->sdma.num_inst_per_aid == i) { in amdgpu_sdma_init_microcode()
269 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; in amdgpu_sdma_init_microcode()
270 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; in amdgpu_sdma_init_microcode()
271 info->fw = adev->sdma.instance[i].fw; in amdgpu_sdma_init_microcode()
272 adev->firmware.fw_size += in amdgpu_sdma_init_microcode()
273 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); in amdgpu_sdma_init_microcode()
279 adev->sdma.instance[0].fw->data; in amdgpu_sdma_init_microcode()
280 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0]; in amdgpu_sdma_init_microcode()
281 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0; in amdgpu_sdma_init_microcode()
282 info->fw = adev->sdma.instance[0].fw; in amdgpu_sdma_init_microcode()
283 adev->firmware.fw_size += in amdgpu_sdma_init_microcode()
284 ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE); in amdgpu_sdma_init_microcode()
285 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1]; in amdgpu_sdma_init_microcode()
286 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1; in amdgpu_sdma_init_microcode()
287 info->fw = adev->sdma.instance[0].fw; in amdgpu_sdma_init_microcode()
288 adev->firmware.fw_size += in amdgpu_sdma_init_microcode()
289 ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE); in amdgpu_sdma_init_microcode()
293 adev->sdma.instance[0].fw->data; in amdgpu_sdma_init_microcode()
294 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_RS64]; in amdgpu_sdma_init_microcode()
295 info->ucode_id = AMDGPU_UCODE_ID_SDMA_RS64; in amdgpu_sdma_init_microcode()
296 info->fw = adev->sdma.instance[0].fw; in amdgpu_sdma_init_microcode()
297 adev->firmware.fw_size += in amdgpu_sdma_init_microcode()
298 ALIGN(le32_to_cpu(sdma_hv3->ucode_size_bytes), PAGE_SIZE); in amdgpu_sdma_init_microcode()
301 err = -EINVAL; in amdgpu_sdma_init_microcode()
316 /* adev->sdma.ras is NULL, which means sdma does not in amdgpu_sdma_ras_sw_init()
319 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
322 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
326 dev_err(adev->dev, "Failed to register sdma ras block!\n"); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
337 ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init; in amdgpu_sdma_ras_sw_init()
340 if (!ras->ras_block.ras_cb) in amdgpu_sdma_ras_sw_init()
341 ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb; in amdgpu_sdma_ras_sw_init()
358 return -ENODEV; in amdgpu_debugfs_sdma_sched_mask_set()
363 if (adev->sdma.has_page_queue) in amdgpu_debugfs_sdma_sched_mask_set()
371 mask = BIT_ULL(adev->sdma.num_instances * num_ring) - 1; in amdgpu_debugfs_sdma_sched_mask_set()
374 return -EINVAL; in amdgpu_debugfs_sdma_sched_mask_set()
376 for (i = 0; i < adev->sdma.num_instances; ++i) { in amdgpu_debugfs_sdma_sched_mask_set()
377 ring = &adev->sdma.instance[i].ring; in amdgpu_debugfs_sdma_sched_mask_set()
378 if (adev->sdma.has_page_queue) in amdgpu_debugfs_sdma_sched_mask_set()
379 page = &adev->sdma.instance[i].page; in amdgpu_debugfs_sdma_sched_mask_set()
381 ring->sched.ready = true; in amdgpu_debugfs_sdma_sched_mask_set()
383 ring->sched.ready = false; in amdgpu_debugfs_sdma_sched_mask_set()
387 page->sched.ready = true; in amdgpu_debugfs_sdma_sched_mask_set()
389 page->sched.ready = false; in amdgpu_debugfs_sdma_sched_mask_set()
405 return -ENODEV; in amdgpu_debugfs_sdma_sched_mask_get()
410 if (adev->sdma.has_page_queue) in amdgpu_debugfs_sdma_sched_mask_get()
415 for (i = 0; i < adev->sdma.num_instances; ++i) { in amdgpu_debugfs_sdma_sched_mask_get()
416 ring = &adev->sdma.instance[i].ring; in amdgpu_debugfs_sdma_sched_mask_get()
417 if (adev->sdma.has_page_queue) in amdgpu_debugfs_sdma_sched_mask_get()
418 page = &adev->sdma.instance[i].page; in amdgpu_debugfs_sdma_sched_mask_get()
420 if (ring->sched.ready) in amdgpu_debugfs_sdma_sched_mask_get()
426 if (page->sched.ready) in amdgpu_debugfs_sdma_sched_mask_get()
446 struct drm_minor *minor = adev_to_drm(adev)->primary; in amdgpu_debugfs_sdma_sched_mask_init()
447 struct dentry *root = minor->debugfs_root; in amdgpu_debugfs_sdma_sched_mask_init()
450 if (!(adev->sdma.num_instances > 1)) in amdgpu_debugfs_sdma_sched_mask_init()
466 return -ENODEV; in amdgpu_get_sdma_reset_mask()
468 return amdgpu_show_reset_mask(buf, adev->sdma.supported_reset); in amdgpu_get_sdma_reset_mask()
481 if (adev->sdma.num_instances) { in amdgpu_sdma_sysfs_reset_mask_init()
482 r = device_create_file(adev->dev, &dev_attr_sdma_reset_mask); in amdgpu_sdma_sysfs_reset_mask_init()
495 if (adev->dev->kobj.sd) { in amdgpu_sdma_sysfs_reset_mask_fini()
496 if (adev->sdma.num_instances) in amdgpu_sdma_sysfs_reset_mask_fini()
497 device_remove_file(adev->dev, &dev_attr_sdma_reset_mask); in amdgpu_sdma_sysfs_reset_mask_fini()
503 if (adev->sdma.has_page_queue && in amdgpu_sdma_get_shared_ring()
504 (ring->me < adev->sdma.num_instances) && in amdgpu_sdma_get_shared_ring()
505 (ring == &adev->sdma.instance[ring->me].ring)) in amdgpu_sdma_get_shared_ring()
506 return &adev->sdma.instance[ring->me].page; in amdgpu_sdma_get_shared_ring()
512 * amdgpu_sdma_is_shared_inv_eng - Check if a ring is an SDMA ring that shares a VM invalidation eng…
516 * This function checks if the given ring is an SDMA ring that shares a VM invalidation engine.
521 int i = ring->me; in amdgpu_sdma_is_shared_inv_eng()
523 if (!adev->sdma.has_page_queue || i >= adev->sdma.num_instances) in amdgpu_sdma_is_shared_inv_eng()
529 return (ring == &adev->sdma.instance[i].page); in amdgpu_sdma_is_shared_inv_eng()
536 struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id]; in amdgpu_sdma_soft_reset()
538 if (sdma_instance->funcs->soft_reset_kernel_queue) in amdgpu_sdma_soft_reset()
539 return sdma_instance->funcs->soft_reset_kernel_queue(adev, instance_id); in amdgpu_sdma_soft_reset()
541 return -EOPNOTSUPP; in amdgpu_sdma_soft_reset()
545 * amdgpu_sdma_reset_engine - Reset a specific SDMA engine
547 * @instance_id: Logical ID of the SDMA engine instance to reset
557 struct amdgpu_sdma_instance *sdma_instance = &adev->sdma.instance[instance_id]; in amdgpu_sdma_reset_engine()
558 struct amdgpu_ring *gfx_ring = &sdma_instance->ring; in amdgpu_sdma_reset_engine()
559 struct amdgpu_ring *page_ring = &sdma_instance->page; in amdgpu_sdma_reset_engine()
561 mutex_lock(&sdma_instance->engine_reset_mutex); in amdgpu_sdma_reset_engine()
568 drm_sched_wqueue_stop(&gfx_ring->sched); in amdgpu_sdma_reset_engine()
570 if (adev->sdma.has_page_queue) in amdgpu_sdma_reset_engine()
571 drm_sched_wqueue_stop(&page_ring->sched); in amdgpu_sdma_reset_engine()
574 if (sdma_instance->funcs->stop_kernel_queue) { in amdgpu_sdma_reset_engine()
575 sdma_instance->funcs->stop_kernel_queue(gfx_ring); in amdgpu_sdma_reset_engine()
576 if (adev->sdma.has_page_queue) in amdgpu_sdma_reset_engine()
577 sdma_instance->funcs->stop_kernel_queue(page_ring); in amdgpu_sdma_reset_engine()
583 dev_err(adev->dev, "Failed to reset SDMA logical instance %u\n", instance_id); in amdgpu_sdma_reset_engine()
587 if (sdma_instance->funcs->start_kernel_queue) { in amdgpu_sdma_reset_engine()
588 sdma_instance->funcs->start_kernel_queue(gfx_ring); in amdgpu_sdma_reset_engine()
589 if (adev->sdma.has_page_queue) in amdgpu_sdma_reset_engine()
590 sdma_instance->funcs->start_kernel_queue(page_ring); in amdgpu_sdma_reset_engine()
601 drm_sched_wqueue_start(&gfx_ring->sched); in amdgpu_sdma_reset_engine()
602 if (adev->sdma.has_page_queue) { in amdgpu_sdma_reset_engine()
604 drm_sched_wqueue_start(&page_ring->sched); in amdgpu_sdma_reset_engine()
608 mutex_unlock(&sdma_instance->engine_reset_mutex); in amdgpu_sdma_reset_engine()