2  * Copyright 2016 Advanced Micro Devices, Inc.
205 	 * Every block in the amdgpu has no-op instructions (e.g., GFX 10
207 	 * etc). This field receives the specific no-op for the component
297  * amdgpu_ring - Holds ring information
353 	 * Some IPs provide support for 64-bit pointers and others for 32-bit
354 	 * only; this behavior is component-specific and defined by the field
355 	 * support_64bit_ptr. If the IP block supports 64-bits, the mask
366 	 * initialization time, and it is defined as (ring_size / 4) -1.
424 #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib)))
425 #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib…
426 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
427 #define amdgpu_ring_test_ib(r, t) ((r)->funcs->test_ib ? (r)->funcs->test_ib((r), (t)) : 0)
428 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
429 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
430 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
431 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
432 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
433 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
434 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (fla…
435 …g_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), …  argument
436 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
437 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
438 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
439 #define amdgpu_ring_emit_gfx_shadow(r, s, c, g, i, v) ((r)->funcs->emit_gfx_shadow((r), (s), (c), (…
440 #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
441 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
442 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
443 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r…
444 #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
445 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
446 #define amdgpu_ring_init_cond_exec(r, a) (r)->funcs->init_cond_exec((r), (a))
447 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
448 #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o)))
449 #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o)))
450 #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o)))
451 #define amdgpu_ring_reset(r, v, f) (r)->funcs->reset((r), (v), (f))
479 	*ring->cond_exe_cpu_addr = cond_exec;  in amdgpu_ring_set_preempt_cond_exec()
484 	memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1);  in amdgpu_ring_clear_ring()
489 	ring->ring[ring->wptr++ & ring->buf_mask] = v;  in amdgpu_ring_write()
490 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write()
491 	ring->count_dw--;  in amdgpu_ring_write()
499 	occupied = ring->wptr & ring->buf_mask;  in amdgpu_ring_write_multiple()
500 	chunk1 = ring->buf_mask + 1 - occupied;  in amdgpu_ring_write_multiple()
502 	chunk2 = count_dw - chunk1;  in amdgpu_ring_write_multiple()
507 		memcpy(&ring->ring[occupied], src, chunk1);  in amdgpu_ring_write_multiple()
511 		memcpy(ring->ring, src, chunk2);  in amdgpu_ring_write_multiple()
514 	ring->wptr += count_dw;  in amdgpu_ring_write_multiple()
515 	ring->wptr &= ring->ptr_mask;  in amdgpu_ring_write_multiple()
516 	ring->count_dw -= count_dw;  in amdgpu_ring_write_multiple()
520  * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute
531 	if (!ring->funcs->init_cond_exec)  in amdgpu_ring_patch_cond_exec()
534 	WARN_ON(offset > ring->buf_mask);  in amdgpu_ring_patch_cond_exec()
535 	WARN_ON(ring->ring[offset] != 0);  in amdgpu_ring_patch_cond_exec()
537 	cur = (ring->wptr - 1) & ring->buf_mask;  in amdgpu_ring_patch_cond_exec()
539 		cur += ring->ring_size >> 2;  in amdgpu_ring_patch_cond_exec()
540 	ring->ring[offset] = cur - offset;  in amdgpu_ring_patch_cond_exec()
552 	return ib->ptr[idx];  in amdgpu_ib_get_value()
558 	ib->ptr[idx] = value;  in amdgpu_ib_set_value()