Lines Matching defs:ucode

706 		   struct amdgpu_firmware_info *ucode,
759 		if (ucode)
761 				 "failed to load ucode %s(0x%X) ",
762 				 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
774 		if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
780 	if (ucode) {
781 		ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
782 		ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
1918 		dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
2101 		dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
2175 		dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
2246 		dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
2349 			 "SECUREDISPLAY: optional securedisplay ta ucode is not available\n");
2633 int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2636 	switch (ucode->ucode_id) {
2860 			     struct amdgpu_firmware_info *ucode)
2865 	switch (ucode->ucode_id) {
2875 			adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2910 				       struct amdgpu_firmware_info *ucode,
2914 	uint64_t fw_mem_mc_addr = ucode->mc_addr;
2919 	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2921 	ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2923 		dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id);
2928 			   struct amdgpu_firmware_info *ucode)
2933 	ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd);
2935 		ret = psp_cmd_submit_buf(psp, ucode, cmd,
2948 	struct amdgpu_firmware_info *ucode =
2949 		&adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
2963 	if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2966 	ret = psp_execute_ip_fw_load(psp, ucode);
2975 	struct amdgpu_firmware_info *ucode =
2976 			&adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2987 	if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2998 	ret = psp_execute_ip_fw_load(psp, ucode);
3007 			       struct amdgpu_firmware_info *ucode)
3009 	if (!ucode->fw || !ucode->ucode_size)
3012 	if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE)
3015 	if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
3022 	    amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
3026 	    (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
3027 	     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
3038 	struct amdgpu_firmware_info *ucode;
3041 		ucode = ucode_list[i];
3042 		psp_print_fw_hdr(psp, ucode);
3043 		ret = psp_execute_ip_fw_load(psp, ucode);
3053 	struct amdgpu_firmware_info *ucode;
3067 		ucode = &adev->firmware.ucode[i];
3069 		if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
3070 		    !fw_load_skip_check(psp, ucode)) {
3077 		if (fw_load_skip_check(psp, ucode))
3091 		    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
3092 		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
3093 		     ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
3099 		/* IMU ucode is part of IFWI and MP0 15.0.8 would load it */
3102 		    (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I ||
3103 		    ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D))
3106 		psp_print_fw_hdr(psp, ucode);
3108 		ret = psp_execute_ip_fw_load(psp, ucode);
3113 		if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
4032 	info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];