Lines Matching refs:uint32_t
85 uint32_t sched_version;
86 uint32_t kiq_version;
87 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
90 uint32_t total_max_queue;
91 uint32_t max_doorbell_slices;
104 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
110 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
120 uint32_t vmid_mask_gfxhub;
121 uint32_t vmid_mask_mmhub;
122 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
123 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
124 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
125 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
127 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES];
130 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES];
134 uint32_t saved_flags;
138 uint32_t xcc_id);
140 uint32_t xcc_id);
143 uint32_t db_start_dw_offset;
144 uint32_t num_mes_dbs;
148 uint32_t event_log_size;
179 uint32_t *ctx_array_size_cpu_ptr;
181 uint32_t proc_ctx_array_size;
183 uint32_t gang_ctx_array_size;
184 uint32_t gang_ctx_array_index;
235 uint32_t queue_size;
237 uint32_t hqd_pipe_priority;
238 uint32_t hqd_queue_priority;
246 uint32_t priority;
247 uint32_t gang_quantum;
248 uint32_t inprocess_gang_priority;
249 uint32_t priority_level;
254 uint32_t xcc_id;
255 uint32_t process_id;
263 uint32_t inprocess_gang_priority;
264 uint32_t gang_global_priority_level;
265 uint32_t doorbell_offset;
269 uint32_t queue_type;
270 uint32_t paging;
271 uint32_t gws_base;
272 uint32_t gws_size;
275 uint32_t trap_en;
276 uint32_t skip_process_ctx_clear;
277 uint32_t is_kfd_process;
278 uint32_t is_aql_queue;
279 uint32_t queue_size;
280 uint32_t exclusively_scheduled;
281 uint32_t sh_mem_config_data;
282 uint32_t vm_cntx_cntl;
283 uint32_t process_context_array_index;
284 uint32_t gang_context_array_index;
288 uint32_t xcc_id;
289 uint32_t doorbell_offset;
291 uint32_t queue_type;
293 uint32_t gang_context_array_index;
297 uint32_t xcc_id;
298 uint32_t queue_type;
299 uint32_t doorbell_offset;
300 uint32_t pipe_id;
301 uint32_t queue_id;
307 uint32_t xcc_id;
309 uint32_t queue_type;
310 uint32_t doorbell_offset;
311 uint32_t pipe_id;
312 uint32_t queue_id;
318 uint32_t xcc_id;
323 uint32_t suspend_fence_value;
324 uint32_t doorbell_offset;
328 uint32_t xcc_id;
331 uint32_t doorbell_offset;
335 uint32_t xcc_id;
336 uint32_t queue_type;
337 uint32_t doorbell_offset;
339 uint32_t me_id;
340 uint32_t pipe_id;
341 uint32_t queue_id;
344 uint32_t vmid;
356 uint32_t xcc_id;
372 uint32_t xcc_id;
377 uint32_t reg_offset;
382 uint32_t reg_offset;
383 uint32_t reg_value;
387 uint32_t ref;
388 uint32_t mask;
389 uint32_t reg0;
390 uint32_t reg1;
397 uint32_t single_memop : 1;
398 uint32_t single_alu_op : 1;
399 uint32_t reserved: 29;
400 uint32_t process_ctx_flush: 1;
402 uint32_t u32all;
404 uint32_t spi_gdbg_per_vmid_cntl;
405 uint32_t tcp_watch_cntl[4];
406 uint32_t trap_en;
412 uint32_t limit_single_process : 1;
413 uint32_t enable_hws_logging_buffer : 1;
414 uint32_t reserved : 30;
416 uint32_t all;
419 uint32_t tdr_level;
420 uint32_t tdr_delay;
470 uint32_t queue_size;
472 uint32_t doorbell_index;
474 uint32_t hqd_pipe_priority;
475 uint32_t hqd_queue_priority;
476 uint32_t mqd_stride_size;
485 uint32_t *cu_mask;
486 uint32_t cu_mask_count;
487 uint32_t cu_flags;
519 struct amdgpu_ring *ring, uint32_t xcc_id);
523 u64 gpu_addr, u64 seq, uint32_t xcc_id);
528 uint32_t xcc_id);
535 uint32_t xcc_id);
547 uint32_t xcc_id);
549 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg,
550 uint32_t xcc_id);
552 uint32_t reg, uint32_t val, uint32_t xcc_id);
554 uint32_t reg0, uint32_t reg1,
555 uint32_t ref, uint32_t mask, uint32_t xcc_id);
559 uint32_t spi_gdbg_per_vmid_cntl,
560 const uint32_t *tcp_watch_cntl,
561 uint32_t flags,
563 uint32_t xcc_id);
565 uint64_t process_context_addr, uint32_t xcc_id);
567 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
639 uint32_t *index);
641 uint32_t index);
643 uint32_t *index);
645 uint32_t index);