Lines Matching refs:amdgpu_device

67 	struct amdgpu_device            *adev;
129 	int                             (*kiq_hw_init)(struct amdgpu_device *adev);
130 	int                             (*kiq_hw_fini)(struct amdgpu_device *adev);
401 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
402 int amdgpu_mes_init(struct amdgpu_device *adev);
403 void amdgpu_mes_fini(struct amdgpu_device *adev);
405 int amdgpu_mes_suspend(struct amdgpu_device *adev);
406 int amdgpu_mes_resume(struct amdgpu_device *adev);
408 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
410 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
414 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
419 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev);
420 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
426 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
427 int amdgpu_mes_wreg(struct amdgpu_device *adev,
429 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
432 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev);
433 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
439 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
442 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
445 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
505 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
507 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev);