108 	int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;  in amdgpu_mes_init()
109 	u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me,  in amdgpu_mes_init()
110 				adev->gfx.me.num_queue_per_pipe,  in amdgpu_mes_init()
111 				adev->gfx.disable_kq ? 0 : adev->gfx.num_gfx_rings);  in amdgpu_mes_init()
112 	u32 compute_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.mec.num_pipe_per_mec,  in amdgpu_mes_init()
113 				adev->gfx.mec.num_queue_per_pipe,  in amdgpu_mes_init()
114 				adev->gfx.disable_kq ? 0 : adev->gfx.num_compute_rings);  in amdgpu_mes_init()
132 	num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me;  in amdgpu_mes_init()
144 	num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec;  in amdgpu_mes_init()
156 		if (i >= adev->gfx.mec.num_pipe_per_mec)  in amdgpu_mes_init()
254 		adev->gfx.mec.mes_hung_db_array =  in amdgpu_mes_init()
258 		if (!adev->gfx.mec.mes_hung_db_array) {  in amdgpu_mes_init()
289 	int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;  in amdgpu_mes_fini()
291 	kfree(adev->gfx.mec.mes_hung_db_array);  in amdgpu_mes_fini()
673 	if (!adev->gfx.funcs->get_hdp_flush_mask) {  in amdgpu_mes_hdp_flush()
682 	adev->gfx.funcs->get_hdp_flush_mask(mes_ring, &ref_and_mask, &reg_mem_engine);  in amdgpu_mes_hdp_flush()
915 	if (adev->enable_mes && adev->gfx.enable_cleaner_shader) {  in amdgpu_mes_update_enforce_isolation()