Lines Matching defs:mes
45 struct amdgpu_mes *mes = &adev->mes;
48 mes->doorbell_bitmap = bitmap_zalloc(PAGE_SIZE / sizeof(u32), GFP_KERNEL);
49 if (!mes->doorbell_bitmap) {
54 mes->num_mes_dbs = PAGE_SIZE / AMDGPU_ONE_DOORBELL_SIZE;
56 adev->mes.aggregated_doorbells[i] = mes->db_start_dw_offset + i * 2;
57 set_bit(i, mes->doorbell_bitmap);
70 r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE,
72 &adev->mes.event_log_gpu_obj,
73 &adev->mes.event_log_gpu_addr,
74 &adev->mes.event_log_cpu_addr);
80 memset(adev->mes.event_log_cpu_addr, 0, adev->mes.event_log_size);
88 bitmap_free(adev->mes.doorbell_bitmap);
95 adev->mes.adev = adev;
97 idr_init(&adev->mes.pasid_idr);
98 idr_init(&adev->mes.gang_id_idr);
99 idr_init(&adev->mes.queue_id_idr);
100 ida_init(&adev->mes.doorbell_ida);
101 spin_lock_init(&adev->mes.queue_id_lock);
102 mutex_init(&adev->mes.mutex_hidden);
105 spin_lock_init(&adev->mes.ring_lock[i]);
107 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
108 adev->mes.vmid_mask_mmhub = 0xFF00;
109 adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xFFFE : 0xFF00;
127 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE;
134 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2;
145 adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC;
156 adev->mes.sdma_hqd_mask[i] = 0xfc;
160 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]);
167 adev->mes.sch_ctx_gpu_addr[i] =
168 adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4);
169 adev->mes.sch_ctx_ptr[i] =
170 (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]];
173 &adev->mes.query_status_fence_offs[i]);
180 adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr +
181 (adev->mes.query_status_fence_offs[i] * 4);
182 adev->mes.query_status_fence_ptr[i] =
183 (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]];
194 if (adev->mes.hung_queue_db_array_size) {
196 adev->mes.hung_queue_db_array_size * sizeof(u32),
199 &adev->mes.hung_queue_db_array_gpu_obj,
200 &adev->mes.hung_queue_db_array_gpu_addr,
201 &adev->mes.hung_queue_db_array_cpu_addr);
214 if (adev->mes.sch_ctx_ptr[i])
215 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
216 if (adev->mes.query_status_fence_ptr[i])
218 adev->mes.query_status_fence_offs[i]);
221 idr_destroy(&adev->mes.pasid_idr);
222 idr_destroy(&adev->mes.gang_id_idr);
223 idr_destroy(&adev->mes.queue_id_idr);
224 ida_destroy(&adev->mes.doorbell_ida);
225 mutex_destroy(&adev->mes.mutex_hidden);
233 amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj,
234 &adev->mes.hung_queue_db_array_gpu_addr,
235 &adev->mes.hung_queue_db_array_cpu_addr);
237 amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj,
238 &adev->mes.event_log_gpu_addr,
239 &adev->mes.event_log_cpu_addr);
242 if (adev->mes.sch_ctx_ptr[i])
243 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
244 if (adev->mes.query_status_fence_ptr[i])
246 adev->mes.query_status_fence_offs[i]);
251 idr_destroy(&adev->mes.pasid_idr);
252 idr_destroy(&adev->mes.gang_id_idr);
253 idr_destroy(&adev->mes.queue_id_idr);
254 ida_destroy(&adev->mes.doorbell_ida);
255 mutex_destroy(&adev->mes.mutex_hidden);
273 amdgpu_mes_lock(&adev->mes);
274 r = adev->mes.funcs->suspend_gang(&adev->mes, &input);
275 amdgpu_mes_unlock(&adev->mes);
297 amdgpu_mes_lock(&adev->mes);
298 r = adev->mes.funcs->resume_gang(&adev->mes, &input);
299 amdgpu_mes_unlock(&adev->mes);
321 amdgpu_mes_lock(&adev->mes);
322 r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input);
323 amdgpu_mes_unlock(&adev->mes);
346 amdgpu_mes_lock(&adev->mes);
347 r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input);
348 amdgpu_mes_unlock(&adev->mes);
378 amdgpu_mes_lock(&adev->mes);
379 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input);
380 amdgpu_mes_unlock(&adev->mes);
389 return adev->mes.hung_queue_db_array_size;
400 u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr;
412 memset(adev->mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET,
413 adev->mes.hung_queue_db_array_size * sizeof(u32));
417 r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes,
423 for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) {
448 dev_err(adev->dev, "critical bug! too many mes readers\n");
457 if (!adev->mes.funcs->misc_op) {
458 dev_err(adev->dev, "mes rreg is not supported!\n");
462 amdgpu_mes_lock(&adev->mes);
463 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
464 amdgpu_mes_unlock(&adev->mes);
486 if (!adev->mes.funcs->misc_op) {
487 dev_err(adev->dev, "mes wreg is not supported!\n");
492 amdgpu_mes_lock(&adev->mes);
493 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
494 amdgpu_mes_unlock(&adev->mes);
515 if (!adev->mes.funcs->misc_op) {
516 dev_err(adev->dev, "mes reg_write_reg_wait is not supported!\n");
521 amdgpu_mes_lock(&adev->mes);
522 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
523 amdgpu_mes_unlock(&adev->mes);
553 if (!adev->mes.funcs->misc_op) {
555 "mes set shader debugger is not supported!\n");
571 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
575 amdgpu_mes_lock(&adev->mes);
577 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
581 amdgpu_mes_unlock(&adev->mes);
592 if (!adev->mes.funcs->misc_op) {
594 "mes flush shader debugger is not supported!\n");
602 amdgpu_mes_lock(&adev->mes);
604 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
608 amdgpu_mes_unlock(&adev->mes);
616 return adev->mes.aggregated_doorbells[prio];
646 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], AMDGPU_UCODE_REQUIRED,
650 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],
659 adev->mes.fw[pipe]->data;
660 adev->mes.uc_start_addr[pipe] =
663 adev->mes.data_start_addr[pipe] =
666 ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data +
668 adev->mes.fw_version[pipe] =
684 info->fw = adev->mes.fw[pipe];
691 info->fw = adev->mes.fw[pipe];
699 amdgpu_ucode_release(&adev->mes.fw[pipe]);
705 uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
723 if (!adev->mes.funcs->misc_op) {
724 dev_err(adev->dev, "mes change config is not supported!\n");
729 amdgpu_mes_lock(&adev->mes);
730 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
731 amdgpu_mes_unlock(&adev->mes);
761 uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);
764 mem, adev->mes.event_log_size, false);