Lines Matching refs:dev_info
899 struct drm_amdgpu_info_device *dev_info; in amdgpu_info_ioctl() local
903 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); in amdgpu_info_ioctl()
904 if (!dev_info) in amdgpu_info_ioctl()
907 dev_info->device_id = adev->pdev->device; in amdgpu_info_ioctl()
908 dev_info->chip_rev = adev->rev_id; in amdgpu_info_ioctl()
909 dev_info->external_rev = adev->external_rev_id; in amdgpu_info_ioctl()
910 dev_info->pci_rev = adev->pdev->revision; in amdgpu_info_ioctl()
911 dev_info->family = adev->family; in amdgpu_info_ioctl()
912 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; in amdgpu_info_ioctl()
913 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
915 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; in amdgpu_info_ioctl()
917 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; in amdgpu_info_ioctl()
918 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; in amdgpu_info_ioctl()
919 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; in amdgpu_info_ioctl()
920 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; in amdgpu_info_ioctl()
922 dev_info->max_engine_clock = in amdgpu_info_ioctl()
923 dev_info->min_engine_clock = in amdgpu_info_ioctl()
925 dev_info->max_memory_clock = in amdgpu_info_ioctl()
926 dev_info->min_memory_clock = in amdgpu_info_ioctl()
929 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; in amdgpu_info_ioctl()
930 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * in amdgpu_info_ioctl()
932 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; in amdgpu_info_ioctl()
933 dev_info->ids_flags = 0; in amdgpu_info_ioctl()
935 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; in amdgpu_info_ioctl()
937 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; in amdgpu_info_ioctl()
939 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; in amdgpu_info_ioctl()
941 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; in amdgpu_info_ioctl()
945 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_GANG_SUBMIT; in amdgpu_info_ioctl()
948 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << in amdgpu_info_ioctl()
952 dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << in amdgpu_info_ioctl()
964 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_BOTTOM; in amdgpu_info_ioctl()
965 dev_info->virtual_address_max = in amdgpu_info_ioctl()
969 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; in amdgpu_info_ioctl()
970 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; in amdgpu_info_ioctl()
972 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); in amdgpu_info_ioctl()
973 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
974 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); in amdgpu_info_ioctl()
975 dev_info->cu_active_number = adev->gfx.cu_info.number; in amdgpu_info_ioctl()
976 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; in amdgpu_info_ioctl()
977 dev_info->ce_ram_size = adev->gfx.ce_ram_size; in amdgpu_info_ioctl()
978 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], in amdgpu_info_ioctl()
980 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], in amdgpu_info_ioctl()
981 sizeof(dev_info->cu_bitmap)); in amdgpu_info_ioctl()
982 dev_info->vram_type = adev->gmc.vram_type; in amdgpu_info_ioctl()
983 dev_info->vram_bit_width = adev->gmc.vram_width; in amdgpu_info_ioctl()
984 dev_info->vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
985 dev_info->gc_double_offchip_lds_buf = in amdgpu_info_ioctl()
987 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; in amdgpu_info_ioctl()
988 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; in amdgpu_info_ioctl()
989 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; in amdgpu_info_ioctl()
990 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; in amdgpu_info_ioctl()
991 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; in amdgpu_info_ioctl()
992 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; in amdgpu_info_ioctl()
993 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; in amdgpu_info_ioctl()
996 dev_info->pa_sc_tile_steering_override = in amdgpu_info_ioctl()
999 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; in amdgpu_info_ioctl()
1006 dev_info->pcie_gen = fls(pcie_gen_mask); in amdgpu_info_ioctl()
1007 dev_info->pcie_num_lanes = in amdgpu_info_ioctl()
1015 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; in amdgpu_info_ioctl()
1016 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; in amdgpu_info_ioctl()
1017 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; in amdgpu_info_ioctl()
1018 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; in amdgpu_info_ioctl()
1019 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * in amdgpu_info_ioctl()
1021 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; in amdgpu_info_ioctl()
1022 dev_info->mall_size = adev->gmc.mall_size; in amdgpu_info_ioctl()
1030 dev_info->shadow_size = shadow_info.shadow_size; in amdgpu_info_ioctl()
1031 dev_info->shadow_alignment = shadow_info.shadow_alignment; in amdgpu_info_ioctl()
1032 dev_info->csa_size = shadow_info.csa_size; in amdgpu_info_ioctl()
1033 dev_info->csa_alignment = shadow_info.csa_alignment; in amdgpu_info_ioctl()
1037 dev_info->userq_ip_mask = amdgpu_userq_get_supported_ip_mask(adev); in amdgpu_info_ioctl()
1039 ret = copy_to_user(out, dev_info, in amdgpu_info_ioctl()
1040 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; in amdgpu_info_ioctl()
1041 kfree(dev_info); in amdgpu_info_ioctl()