45  * command ring and the hw will fetch the commands from the IB
48  * put in IBs for execution by the requested ring.
103  * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
105  * @ring: ring index the IB is associated with
111  * Schedule an IB on the associated ring (all asics).
114  * On SI, there are two parallel engines fed from the primary ring,
121  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
124 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,  in amdgpu_ib_schedule()  argument
128 	struct amdgpu_device *adev = ring->adev;  in amdgpu_ib_schedule()
148 	/* ring tests don't use a job */  in amdgpu_ib_schedule()
159 		 * The driver needs this so it can skip the ring  in amdgpu_ib_schedule()
173 	if (!ring->sched.ready) {  in amdgpu_ib_schedule()
174 		dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);  in amdgpu_ib_schedule()
184 	    (!ring->funcs->secure_submission_supported)) {  in amdgpu_ib_schedule()
185 		dev_err(adev->dev, "secure submissions not supported on ring <%s>\n", ring->name);  in amdgpu_ib_schedule()
189 	alloc_size = ring->funcs->emit_frame_size + num_ibs *  in amdgpu_ib_schedule()
190 		ring->funcs->emit_ib_size;  in amdgpu_ib_schedule()
192 	r = amdgpu_ring_alloc(ring, alloc_size);  in amdgpu_ib_schedule()
198 	need_ctx_switch = ring->current_ctx != fence_ctx;  in amdgpu_ib_schedule()
199 	if (ring->funcs->emit_pipeline_sync && job &&  in amdgpu_ib_schedule()
201 	     need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {  in amdgpu_ib_schedule()
211 	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)  in amdgpu_ib_schedule()
212 		ring->funcs->emit_mem_sync(ring);  in amdgpu_ib_schedule()
214 	if (ring->funcs->emit_wave_limit &&  in amdgpu_ib_schedule()
215 	    ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)  in amdgpu_ib_schedule()
216 		ring->funcs->emit_wave_limit(ring, true);  in amdgpu_ib_schedule()
218 	if (ring->funcs->insert_start)  in amdgpu_ib_schedule()
219 		ring->funcs->insert_start(ring);  in amdgpu_ib_schedule()
222 		r = amdgpu_vm_flush(ring, job, need_pipe_sync);  in amdgpu_ib_schedule()
224 			amdgpu_ring_undo(ring);  in amdgpu_ib_schedule()
229 	amdgpu_ring_ib_begin(ring);  in amdgpu_ib_schedule()
231 	if (ring->funcs->emit_gfx_shadow)  in amdgpu_ib_schedule()
232 		amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,  in amdgpu_ib_schedule()
235 	if (ring->funcs->init_cond_exec)  in amdgpu_ib_schedule()
236 		cond_exec = amdgpu_ring_init_cond_exec(ring,  in amdgpu_ib_schedule()
237 						       ring->cond_exe_gpu_addr);  in amdgpu_ib_schedule()
239 	amdgpu_device_flush_hdp(adev, ring);  in amdgpu_ib_schedule()
244 	if (job && ring->funcs->emit_cntxcntl) {  in amdgpu_ib_schedule()
247 		amdgpu_ring_emit_cntxcntl(ring, status);  in amdgpu_ib_schedule()
253 	if (job && ring->funcs->emit_frame_cntl) {  in amdgpu_ib_schedule()
255 		amdgpu_ring_emit_frame_cntl(ring, true, secure);  in amdgpu_ib_schedule()
261 		if (job && ring->funcs->emit_frame_cntl) {  in amdgpu_ib_schedule()
263 				amdgpu_ring_emit_frame_cntl(ring, false, secure);  in amdgpu_ib_schedule()
265 				amdgpu_ring_emit_frame_cntl(ring, true, secure);  in amdgpu_ib_schedule()
269 		amdgpu_ring_emit_ib(ring, job, ib, status);  in amdgpu_ib_schedule()
273 	if (job && ring->funcs->emit_frame_cntl)  in amdgpu_ib_schedule()
274 		amdgpu_ring_emit_frame_cntl(ring, false, secure);  in amdgpu_ib_schedule()
276 	amdgpu_device_invalidate_hdp(adev, ring);  in amdgpu_ib_schedule()
283 		amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,  in amdgpu_ib_schedule()
287 	if (ring->funcs->emit_gfx_shadow && ring->funcs->init_cond_exec) {  in amdgpu_ib_schedule()
288 		amdgpu_ring_emit_gfx_shadow(ring, 0, 0, 0, false, 0);  in amdgpu_ib_schedule()
289 		amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr);  in amdgpu_ib_schedule()
292 	r = amdgpu_fence_emit(ring, f, af, fence_flags);  in amdgpu_ib_schedule()
296 			amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid);  in amdgpu_ib_schedule()
297 		amdgpu_ring_undo(ring);  in amdgpu_ib_schedule()
301 	if (ring->funcs->insert_end)  in amdgpu_ib_schedule()
302 		ring->funcs->insert_end(ring);  in amdgpu_ib_schedule()
304 	amdgpu_ring_patch_cond_exec(ring, cond_exec);  in amdgpu_ib_schedule()
306 	ring->current_ctx = fence_ctx;  in amdgpu_ib_schedule()
307 	if (job && ring->funcs->emit_switch_buffer)  in amdgpu_ib_schedule()
308 		amdgpu_ring_emit_switch_buffer(ring);  in amdgpu_ib_schedule()
310 	if (ring->funcs->emit_wave_limit &&  in amdgpu_ib_schedule()
311 	    ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)  in amdgpu_ib_schedule()
312 		ring->funcs->emit_wave_limit(ring, false);  in amdgpu_ib_schedule()
322 	amdgpu_ring_ib_end(ring);  in amdgpu_ib_schedule()
323 	amdgpu_ring_commit(ring);  in amdgpu_ib_schedule()
386  * Test an IB (Indirect Buffer) on each ring.
387  * If the test fails, disable the ring.
388  * Returns 0 on success, error if the primary GFX ring
419 		struct amdgpu_ring *ring = adev->rings[i];  in amdgpu_ib_ring_tests()  local
425 		if (!ring->sched.ready || !ring->funcs->test_ib)  in amdgpu_ib_ring_tests()
429 		    ring->funcs->type == AMDGPU_RING_TYPE_KIQ)  in amdgpu_ib_ring_tests()
433 		if (ring->funcs->type == AMDGPU_RING_TYPE_UVD ||  in amdgpu_ib_ring_tests()
434 			ring->funcs->type == AMDGPU_RING_TYPE_VCE ||  in amdgpu_ib_ring_tests()
435 			ring->funcs->type == AMDGPU_RING_TYPE_UVD_ENC ||  in amdgpu_ib_ring_tests()
436 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_DEC ||  in amdgpu_ib_ring_tests()
437 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||  in amdgpu_ib_ring_tests()
438 			ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)  in amdgpu_ib_ring_tests()
443 		r = amdgpu_ring_test_ib(ring, tmo);  in amdgpu_ib_ring_tests()
446 				      ring->name);  in amdgpu_ib_ring_tests()
450 		ring->sched.ready = false;  in amdgpu_ib_ring_tests()
452 			  ring->name, r);  in amdgpu_ib_ring_tests()
454 		if (ring == &adev->gfx.gfx_ring[0]) {  in amdgpu_ib_ring_tests()