Lines Matching defs:gmc
46 return adev->gmc.xgmi.connected_to_cpu || amdgpu_virt_xgmi_migrate_enabled(adev);
61 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
62 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
75 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
79 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
83 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
86 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
90 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
94 amdgpu_bo_unpin(adev->gmc.pdb0_bo);
96 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
98 amdgpu_bo_unref(&adev->gmc.pdb0_bo);
173 value = addr & adev->gmc.pte_addr_mask;
198 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
201 return adev->gmc.agp_start + bo->ttm->dma_address[0];
286 adev->gmc.gart_size =
289 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
308 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
434 struct amdgpu_gmc *gmc = &adev->gmc;
446 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
451 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
472 fault = &gmc->fault_ring[fault->next];
480 fault = &gmc->fault_ring[gmc->last_fault];
485 fault->next = gmc->fault_hash[hash].idx;
486 gmc->fault_hash[hash].idx = gmc->last_fault++;
503 struct amdgpu_gmc *gmc = &adev->gmc;
529 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
541 fault = &gmc->fault_ring[fault->next];
731 if (adev->gmc.flush_tlb_needs_extra_type_2)
732 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid,
735 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2)
736 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid,
739 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, vmid, vmhub,
793 if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) {
795 if (!adev->gmc.gmc_funcs->flush_gpu_tlb_pasid) {
800 if (adev->gmc.flush_tlb_needs_extra_type_2)
801 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
805 if (adev->gmc.flush_tlb_needs_extra_type_0 && flush_type == 2)
806 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
810 adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,
818 if (adev->gmc.flush_tlb_needs_extra_type_2)
821 if (adev->gmc.flush_tlb_needs_extra_type_0)
830 if (adev->gmc.flush_tlb_needs_extra_type_2)
833 if (flush_type == 2 && adev->gmc.flush_tlb_needs_extra_type_0)
942 adev->gmc.tmz_enabled = false;
946 adev->gmc.tmz_enabled = true;
976 adev->gmc.tmz_enabled = false;
980 adev->gmc.tmz_enabled = true;
986 adev->gmc.tmz_enabled = false;
1002 struct amdgpu_gmc *gmc = &adev->gmc;
1017 gmc->noretry = 1;
1019 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
1051 if (adev->gmc.is_app_apu)
1092 (adev->gmc.vram_start == 0))
1106 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1143 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
1144 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
1155 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
1160 vram_addr -= adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1167 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
1176 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
1189 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
1275 for_each_inst(mode, adev->gmc.supported_nps_modes) {
1295 for_each_inst(i, adev->gmc.supported_nps_modes) {
1305 if (mode == adev->gmc.gmc_funcs->query_mem_partition_mode(adev)) {
1320 adev->gmc.requested_nps_mode = mode;
1341 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
1357 if (!adev->gmc.gmc_funcs->query_mem_partition_mode)
1360 nps_switch_support = (hweight32(adev->gmc.supported_nps_modes &
1378 if (!adev->gmc.gmc_funcs->query_mem_partition_mode)
1398 (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS);
1484 return (((BIT(req_nps_mode) & adev->gmc.supported_nps_modes) ==
1494 if (amdgpu_sriov_vf(adev) || !adev->gmc.supported_nps_modes ||
1495 !adev->gmc.gmc_funcs->request_mem_partition_mode)
1498 cur_nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
1512 req_nps_mode = adev->gmc.requested_nps_mode;
1517 r = adev->gmc.gmc_funcs->request_mem_partition_mode(adev, req_nps_mode);
1529 if (adev->gmc.gmc_funcs->need_reset_on_init)
1530 return adev->gmc.gmc_funcs->need_reset_on_init(adev);
1538 switch (adev->gmc.num_mem_partitions) {
1594 valid = (adev->gmc.num_mem_partitions == 1);
1597 valid = (adev->gmc.num_mem_partitions == 2);
1600 valid = (adev->gmc.num_mem_partitions == 3 ||
1601 adev->gmc.num_mem_partitions == 4);
1604 valid = (adev->gmc.num_mem_partitions == 8);
1660 adev->gmc.num_mem_partitions = num_ranges;
1674 adev->gmc.num_mem_partitions = 0;
1677 adev->gmc.num_mem_partitions = 1;
1680 adev->gmc.num_mem_partitions = 2;
1684 adev->gmc.num_mem_partitions = 3;
1686 adev->gmc.num_mem_partitions = 4;
1689 adev->gmc.num_mem_partitions = 8;
1692 adev->gmc.num_mem_partitions = 1;
1698 &adev->gmc.num_mem_partitions);
1701 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) {
1708 if (!adev->gmc.num_mem_partitions) {
1711 adev->gmc.num_mem_partitions = 1;
1714 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT;
1715 size /= adev->gmc.num_mem_partitions;
1717 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
1725 l = adev->gmc.num_mem_partitions - 1;
1730 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
1732 adev->gmc.real_vram_size -
1740 adev->gmc.mem_partitions = kzalloc_objs(struct amdgpu_mem_partition_info,
1742 if (!adev->gmc.mem_partitions)
1745 if (adev->gmc.is_app_apu)
1746 amdgpu_gmc_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
1748 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
1758 if (!adev->gmc.num_mem_partitions) {
1760 kfree(adev->gmc.mem_partitions);
1761 adev->gmc.mem_partitions = NULL;