60  * - 3.0.0 - initial driver
61  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
62  * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
64  * - 3.3.0 - Add VM support for UVD on supported hardware.
65  * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
66  * - 3.5.0 - Add support for new UVD_NO_OP register.
67  * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
68  * - 3.7.0 - Add support for VCE clock list packet
69  * - 3.8.0 - Add support raster config init in the kernel
70  * - 3.9.0 - Add support for memory query info about VRAM and GTT.
71  * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
72  * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
73  * - 3.12.0 - Add query for double offchip LDS buffers
74  * - 3.13.0 - Add PRT support
75  * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
76  * - 3.15.0 - Export more gpu info for gfx9
77  * - 3.16.0 - Add reserved vmid support
78  * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
79  * - 3.18.0 - Export gpu always on cu bitmap
80  * - 3.19.0 - Add support for UVD MJPEG decode
81  * - 3.20.0 - Add support for local BOs
82  * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
83  * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
84  * - 3.23.0 - Add query for VRAM lost counter
85  * - 3.24.0 - Add high priority compute support for gfx9
86  * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
87  * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
88  * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
89  * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
90  * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
91  * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
92  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
93  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
94  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
95  * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
96  * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
97  * - 3.36.0 - Allow reading more status registers on si/cik
98  * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
99  * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
100  * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
101  * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
102  * - 3.41.0 - Add video codec query
103  * - 3.42.0 - Add 16bpc fixed point display support
104  * - 3.43.0 - Add device hot plug/unplug support
105  * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
106  * - 3.45.0 - Add context ioctl stable pstate interface
107  * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
108  * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
109  * - 3.48.0 - Add IP discovery version info to HW INFO
110  * - 3.49.0 - Add gang submit into CS IOCTL
111  * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
113  *   3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
114  *   3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
117  *   3.53.0 - Support for GFX11 CP GFX shadowing
118  *   3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
119  * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
120  * - 3.56.0 - Update IB start address and size alignment for decode and encode
121  * - 3.57.0 - Compute tunneling on GFX10+
122  * - 3.58.0 - Add GFX12 DCC support
123  * - 3.59.0 - Cleared VRAM
124  * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
125  * - 3.61.0 - Contains fix for RV/PCO compute queues
126  * - 3.62.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT
127  * - 3.63.0 - GFX12 display DCC supports 256B max compressed block size
128  * - 3.64.0 - Userq IP support query
153 int amdgpu_gart_size = -1; /* auto */
154 int amdgpu_gtt_size = -1; /* auto */
155 int amdgpu_moverate = -1; /* auto */
156 int amdgpu_audio = -1;
159 int amdgpu_pcie_gen2 = -1;
160 int amdgpu_msi = -1;
162 int amdgpu_dpm = -1;
163 int amdgpu_fw_load_type = -1;
164 int amdgpu_aspm = -1;
165 int amdgpu_runtime_pm = -1;
167 int amdgpu_bapm = -1;
169 int amdgpu_vm_size = -1;
170 int amdgpu_vm_fragment_size = -1;
171 int amdgpu_vm_block_size = -1;
173 int amdgpu_vm_update_mode = -1;
175 int amdgpu_dc = -1;
185 int amdgpu_enforce_isolation = -1;
186 int amdgpu_modeset = -1;
203 int amdgpu_lbpw = -1;
204 int amdgpu_compute_multipipe = -1;
205 int amdgpu_gpu_recovery = -1; /* auto */
208 int amdgpu_smu_pptable_id = -1;
212  *   - With this, for multiple monitors in sync(e.g. with the same model),
223 int amdgpu_mcbp = -1;
224 int amdgpu_discovery = -1;
229 int amdgpu_noretry = -1;
230 int amdgpu_force_asic_type = -1;
231 int amdgpu_tmz = -1; /* auto */
233 int amdgpu_reset_method = -1; /* auto */
234 int amdgpu_num_kcq = -1;
238 int amdgpu_sg_display = -1; /* auto */
241 int amdgpu_seamless = -1; /* auto */
243 int amdgpu_agp = -1; /* auto */
244 int amdgpu_wbrf = -1;
245 int amdgpu_damage_clips = -1; /* auto */
247 int amdgpu_rebar = -1; /* auto */
248 int amdgpu_user_queue = -1;
265 int amdgpu_ras_enable = -1;
267 int amdgpu_bad_page_threshold = -1;
290  * The default is -1 (The size depends on asic).
292 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
298  * The default is -1 (Use value specified by TTM).
301 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
306  * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
308 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disa…
313 …* Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to di…
315 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
320 …play Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto…
322 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
327  * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
334  * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
336 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
341 …gnaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
343 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
357  * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
361  * - With one value specified, the setting will apply to all non-compute jobs.
362  * - With multiple values specified, the first one will be for GFX.
370 …"0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,…
378  * The default is -1 (auto).
380 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
387  * to -1 to select the default loading mode for the ASIC, as defined
388  * by the driver.  The default is -1 (auto).
390 …if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
395  * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
397 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
403  * the dGPUs when they are idle if supported. The default is -1 (auto enable).
405  * Setting the value to -2 is auto enabled with power down when displays are attached.
407 …PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = dis…
423  * The default -1 (auto, enabled)
425 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
430 …* Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disa…
437 …* Override the size of the GPU's per client virtual address space in GiB.  The default is -1 (auto…
444 …* Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for…
451 …le size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each…
466 …* is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, neve…
480 …* Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (a…
482 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
574 …oad Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
576 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)…
579 …_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
584 …* Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disable…
586 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)…
598  * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
600 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (d…
682 …* It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default…
685 	"Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
691  * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
736  * do not support per-process XNACK this also disables retry page faults.
737  * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
740 	"Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
763  * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
764  * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
770 …"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for de…
777 int hws_max_conc_proc = -1;
872  * Enable PCIe P2P (requires large-BAR). Default value: true (on)
877 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
902  * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
903  * default. Values 1-4 control the maximum allowable brightness reduction via
907  * Defaults to -1, or auto. Userspace can only override this level after
908  * boot if it's set to auto.
910 int amdgpu_dm_abm_level = -1;
912 		 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
915 int amdgpu_backlight = -1;
916 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
925  * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
928 		 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
936  * The default value: 0 (off).  TODO: change to auto till it is completed.
938 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
969  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
971 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = m…
980 …ld(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = threshold determin…
1000 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
1025 …"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft p…
1034 	"specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
1046  * (-1 = auto, 0 = disable, 1 = enable, 2 = enable legacy mode, 3 = enable without cleaner shader)
1050 "enforce process isolation between graphics and compute. (-1 = auto, 0 = disable, 1 = enable, 2 = e…
1054  * Override nomodeset (1 = override, -1 = auto). The default is -1 (auto).
1056 MODULE_PARM_DESC(modeset, "Override nomodeset (1 = enable, -1 = auto)");
1063 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
1070  * - 0x1: Debug VM handling
1071  * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1074  * - 0x4: Disable GPU soft recovery, always do a full reset
1075  * - 0x8: Use VRAM for firmware loading
1076  * - 0x10: Enable ACA based RAS logging
1077  * - 0x20: Enable experimental resets
1078  * - 0x40: Disable ring resets
1079  * - 0x80: Use VRAM for SMU pool
1088  * are non-snooped, so they are only used for access to uncached memory.
1090 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1097  * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1099  * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1100  * on active list of frequencies in-use (to be avoided) as part of initial setting or
1101  * P-state transition. However, there may be potential performance impact with this
1103  * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1106 	"Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1116 MODULE_PARM_DESC(rebar, "Resizable BAR (-1 = auto (default), 0 = disable, 1 = enable)");
1123  * - -1 = auto (ASIC specific default)
1124  * -  0 = user queues disabled
1125  * -  1 = user queues enabled and kernel queues enabled (if supported)
1126  * -  2 = user queues enabled and kernel queues disabled
1128 MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 =…
2227 	/* 0 - GPU  in amdgpu_get_secondary_funcs()
2228 	 * 1 - audio  in amdgpu_get_secondary_funcs()
2229 	 * 2 - USB  in amdgpu_get_secondary_funcs()
2230 	 * 3 - UCSI  in amdgpu_get_secondary_funcs()
2233 		p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),  in amdgpu_get_secondary_funcs()
2234 						adev->pdev->bus->number, i);  in amdgpu_get_secondary_funcs()
2236 			pm_runtime_get_sync(&p->dev);  in amdgpu_get_secondary_funcs()
2237 			pm_runtime_mark_last_busy(&p->dev);  in amdgpu_get_secondary_funcs()
2238 			pm_runtime_put_autosuspend(&p->dev);  in amdgpu_get_secondary_funcs()
2248 		adev->debug_vm = true;  in amdgpu_init_debug_options()
2252 		pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");  in amdgpu_init_debug_options()
2253 		adev->debug_largebar = true;  in amdgpu_init_debug_options()
2258 		adev->debug_disable_soft_recovery = true;  in amdgpu_init_debug_options()
2263 		adev->debug_use_vram_fw_buf = true;  in amdgpu_init_debug_options()
2268 		adev->debug_enable_ras_aca = true;  in amdgpu_init_debug_options()
2273 		adev->debug_exp_resets = true;  in amdgpu_init_debug_options()
2278 		adev->debug_disable_gpu_ring_reset = true;  in amdgpu_init_debug_options()
2282 		adev->pm.smu_debug_mask |= SMU_DEBUG_POOL_USE_VRAM;  in amdgpu_init_debug_options()
2286 		adev->debug_vm_userptr = true;  in amdgpu_init_debug_options()
2291 		adev->debug_disable_ce_logs = true;  in amdgpu_init_debug_options()
2296 		adev->debug_enable_ce_cs = true;  in amdgpu_init_debug_options()
2305 		if (pdev->device == asic_type_quirks[i].device &&  in amdgpu_fix_asic_type()
2306 			pdev->revision == asic_type_quirks[i].revision) {  in amdgpu_fix_asic_type()
2321 	unsigned long flags = ent->driver_data;  in amdgpu_pci_probe()
2325 	if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA ||  in amdgpu_pci_probe()
2326 	    (pdev->class >> 8) == PCI_CLASS_DISPLAY_OTHER) {  in amdgpu_pci_probe()
2327 		if (drm_firmware_drivers_only() && amdgpu_modeset == -1)  in amdgpu_pci_probe()
2328 			return -EINVAL;  in amdgpu_pci_probe()
2333 		if (amdgpu_unsupported_pciidlist[i] == pdev->device)  in amdgpu_pci_probe()
2334 			return -ENODEV;  in amdgpu_pci_probe()
2337 	if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))  in amdgpu_pci_probe()
2347 		return -ENODEV;  in amdgpu_pci_probe()
2358 		dev_info(&pdev->dev,  in amdgpu_pci_probe()
2360 		return -ENOTSUPP;  in amdgpu_pci_probe()
2371 			dev_info(&pdev->dev,  in amdgpu_pci_probe()
2373 			dev_info(&pdev->dev,  in amdgpu_pci_probe()
2376 			return -ENODEV;  in amdgpu_pci_probe()
2380 		dev_info(&pdev->dev, "amdgpu is built without SI support.\n");  in amdgpu_pci_probe()
2381 		return -ENODEV;  in amdgpu_pci_probe()
2390 			dev_info(&pdev->dev,  in amdgpu_pci_probe()
2392 			dev_info(&pdev->dev,  in amdgpu_pci_probe()
2395 			return -ENODEV;  in amdgpu_pci_probe()
2399 		dev_info(&pdev->dev, "amdgpu is built without CIK support.\n");  in amdgpu_pci_probe()
2400 		return -ENODEV;  in amdgpu_pci_probe()
2406 	adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);  in amdgpu_pci_probe()
2410 	adev->dev  = &pdev->dev;  in amdgpu_pci_probe()
2411 	adev->pdev = pdev;  in amdgpu_pci_probe()
2415 		ddev->driver_features &= ~DRIVER_ATOMIC;  in amdgpu_pci_probe()
2431 	if (ret == -EAGAIN && ++retry <= 3) {  in amdgpu_pci_probe()
2452 	if (adev->mode_info.mode_config_initialized &&  in amdgpu_pci_probe()
2453 	    !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {  in amdgpu_pci_probe()
2457 		if (adev->gmc.real_vram_size <= (32*1024*1024))  in amdgpu_pci_probe()
2469 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {  in amdgpu_pci_probe()
2472 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);  in amdgpu_pci_probe()
2475 			dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |  in amdgpu_pci_probe()
2478 		pm_runtime_use_autosuspend(ddev->dev);  in amdgpu_pci_probe()
2479 		pm_runtime_set_autosuspend_delay(ddev->dev, 5000);  in amdgpu_pci_probe()
2481 		pm_runtime_allow(ddev->dev);  in amdgpu_pci_probe()
2483 		pm_runtime_mark_last_busy(ddev->dev);  in amdgpu_pci_probe()
2484 		pm_runtime_put_autosuspend(ddev->dev);  in amdgpu_pci_probe()
2491 		 *   - put ASIC into BACO state only when both video and  in amdgpu_pci_probe()
2493 		 *   - pull ASIC out of BACO state when either video or  in amdgpu_pci_probe()
2500 		 * be no PMFW-aware D-state transition(D0->D3) on runpm  in amdgpu_pci_probe()
2504 		 * into D0 state. Then there will be a PMFW-aware D-state  in amdgpu_pci_probe()
2505 		 * transition(D0->D3) on runpm suspend.  in amdgpu_pci_probe()
2508 		    !(adev->flags & AMD_IS_APU) &&  in amdgpu_pci_probe()
2509 		    adev->asic_type >= CHIP_NAVI10)  in amdgpu_pci_probe()
2531 	if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {  in amdgpu_pci_remove()
2532 		pm_runtime_get_sync(dev->dev);  in amdgpu_pci_remove()
2533 		pm_runtime_forbid(dev->dev);  in amdgpu_pci_remove()
2557 	if (adev->in_s4 && adev->in_suspend)  in amdgpu_pci_shutdown()
2566 		adev->mp1_state = PP_MP1_STATE_UNLOAD;  in amdgpu_pci_shutdown()
2568 	adev->mp1_state = PP_MP1_STATE_NONE;  in amdgpu_pci_shutdown()
2577 	if (adev->in_s4 && adev->in_suspend)  in amdgpu_pmops_prepare()
2607 		adev->in_s0ix = true;  in amdgpu_pmops_suspend()
2609 		adev->in_s3 = true;  in amdgpu_pmops_suspend()
2610 	if (!adev->in_s0ix && !adev->in_s3) {  in amdgpu_pmops_suspend()
2613 		if (adev->last_suspend_state != PM_SUSPEND_ON &&  in amdgpu_pmops_suspend()
2614 		    adev->last_suspend_state != pm_suspend_target_state) {  in amdgpu_pmops_suspend()
2617 			return -EINVAL;  in amdgpu_pmops_suspend()
2625 	adev->last_suspend_state = pm_suspend_target_state;  in amdgpu_pmops_suspend()
2638 		amdgpu_device_lock_reset_domain(adev->reset_domain);  in amdgpu_pmops_suspend_noirq()
2640 		amdgpu_device_unlock_reset_domain(adev->reset_domain);  in amdgpu_pmops_suspend_noirq()
2653 	if (!adev->in_s0ix && !adev->in_s3)  in amdgpu_pmops_resume()
2657 	if (!pci_device_is_present(adev->pdev))  in amdgpu_pmops_resume()
2658 		adev->no_hw_access = true;  in amdgpu_pmops_resume()
2662 		adev->in_s0ix = false;  in amdgpu_pmops_resume()
2664 		adev->in_s3 = false;  in amdgpu_pmops_resume()
2700 	if (adev->in_s4 && adev->in_suspend)  in amdgpu_pmops_poweroff()
2719 	if (adev->mode_info.num_crtc) {  in amdgpu_runtime_idle_check_display()
2724 		if (amdgpu_runtime_pm != -2) {  in amdgpu_runtime_idle_check_display()
2730 			mutex_lock(&drm_dev->mode_config.mutex);  in amdgpu_runtime_idle_check_display()
2733 				if (list_connector->status == connector_status_connected) {  in amdgpu_runtime_idle_check_display()
2734 					ret = -EBUSY;  in amdgpu_runtime_idle_check_display()
2739 			mutex_unlock(&drm_dev->mode_config.mutex);  in amdgpu_runtime_idle_check_display()
2745 		if (adev->dc_enabled) {  in amdgpu_runtime_idle_check_display()
2749 				drm_modeset_lock(&crtc->mutex, NULL);  in amdgpu_runtime_idle_check_display()
2750 				if (crtc->state->active)  in amdgpu_runtime_idle_check_display()
2751 					ret = -EBUSY;  in amdgpu_runtime_idle_check_display()
2752 				drm_modeset_unlock(&crtc->mutex);  in amdgpu_runtime_idle_check_display()
2757 			mutex_lock(&drm_dev->mode_config.mutex);  in amdgpu_runtime_idle_check_display()
2758 			drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);  in amdgpu_runtime_idle_check_display()
2762 				if (list_connector->dpms ==  DRM_MODE_DPMS_ON) {  in amdgpu_runtime_idle_check_display()
2763 					ret = -EBUSY;  in amdgpu_runtime_idle_check_display()
2770 			drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);  in amdgpu_runtime_idle_check_display()
2771 			mutex_unlock(&drm_dev->mode_config.mutex);  in amdgpu_runtime_idle_check_display()
2790 	mutex_lock(&adev->userq_mutex);  in amdgpu_runtime_idle_check_userq()
2791 	list_for_each_entry_safe(uqm, tmp, &adev->userq_mgr_list, list) {  in amdgpu_runtime_idle_check_userq()
2792 		idr_for_each_entry(&uqm->userq_idr, queue, queue_id) {  in amdgpu_runtime_idle_check_userq()
2793 			ret = -EBUSY;  in amdgpu_runtime_idle_check_userq()
2798 	mutex_unlock(&adev->userq_mutex);  in amdgpu_runtime_idle_check_userq()
2810 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {  in amdgpu_pmops_runtime_suspend()
2812 		return -EBUSY;  in amdgpu_pmops_runtime_suspend()
2824 		struct amdgpu_ring *ring = adev->rings[i];  in amdgpu_pmops_runtime_suspend()
2826 		if (ring && ring->sched.ready) {  in amdgpu_pmops_runtime_suspend()
2829 				return -EBUSY;  in amdgpu_pmops_runtime_suspend()
2833 	adev->in_runpm = true;  in amdgpu_pmops_runtime_suspend()
2834 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)  in amdgpu_pmops_runtime_suspend()
2835 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;  in amdgpu_pmops_runtime_suspend()
2844 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)  in amdgpu_pmops_runtime_suspend()
2845 		adev->mp1_state = PP_MP1_STATE_UNLOAD;  in amdgpu_pmops_runtime_suspend()
2852 		adev->in_runpm = false;  in amdgpu_pmops_runtime_suspend()
2853 		if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)  in amdgpu_pmops_runtime_suspend()
2854 			adev->mp1_state = PP_MP1_STATE_NONE;  in amdgpu_pmops_runtime_suspend()
2858 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO)  in amdgpu_pmops_runtime_suspend()
2859 		adev->mp1_state = PP_MP1_STATE_NONE;  in amdgpu_pmops_runtime_suspend()
2861 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {  in amdgpu_pmops_runtime_suspend()
2869 		drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;  in amdgpu_pmops_runtime_suspend()
2870 	} else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {  in amdgpu_pmops_runtime_suspend()
2872 	} else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||  in amdgpu_pmops_runtime_suspend()
2873 			(adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {  in amdgpu_pmops_runtime_suspend()
2877 	dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");  in amdgpu_pmops_runtime_suspend()
2889 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)  in amdgpu_pmops_runtime_resume()
2890 		return -EINVAL;  in amdgpu_pmops_runtime_resume()
2893 	if (!pci_device_is_present(adev->pdev))  in amdgpu_pmops_runtime_resume()
2894 		adev->no_hw_access = true;  in amdgpu_pmops_runtime_resume()
2896 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) {  in amdgpu_pmops_runtime_resume()
2897 		drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;  in amdgpu_pmops_runtime_resume()
2908 	} else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) {  in amdgpu_pmops_runtime_resume()
2913 	} else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) ||  in amdgpu_pmops_runtime_resume()
2914 			(adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) {  in amdgpu_pmops_runtime_resume()
2919 		if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)  in amdgpu_pmops_runtime_resume()
2924 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX)  in amdgpu_pmops_runtime_resume()
2925 		drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;  in amdgpu_pmops_runtime_resume()
2926 	adev->in_runpm = false;  in amdgpu_pmops_runtime_resume()
2936 	if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {  in amdgpu_pmops_runtime_idle()
2938 		return -EBUSY;  in amdgpu_pmops_runtime_idle()
2954 	struct drm_file *file_priv = filp->private_data;  in amdgpu_drm_release()
2955 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;  in amdgpu_drm_release()
2956 	struct drm_device *dev = file_priv->minor->dev;  in amdgpu_drm_release()
2960 		fpriv->evf_mgr.fd_closing = true;  in amdgpu_drm_release()
2961 		amdgpu_eviction_fence_destroy(&fpriv->evf_mgr);  in amdgpu_drm_release()
2962 		amdgpu_userq_mgr_fini(&fpriv->userq_mgr);  in amdgpu_drm_release()
2972 	struct drm_file *file_priv = filp->private_data;  in amdgpu_drm_ioctl()
2976 	dev = file_priv->minor->dev;  in amdgpu_drm_ioctl()
2977 	ret = pm_runtime_get_sync(dev->dev);  in amdgpu_drm_ioctl()
2983 	pm_runtime_mark_last_busy(dev->dev);  in amdgpu_drm_ioctl()
2985 	pm_runtime_put_autosuspend(dev->dev);  in amdgpu_drm_ioctl()
3006 	struct drm_file *file_priv = f->private_data;  in amdgpu_flush()
3007 	struct amdgpu_fpriv *fpriv = file_priv->driver_priv;  in amdgpu_flush()
3010 	timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);  in amdgpu_flush()
3011 	timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);  in amdgpu_flush()
3039 		return -EINVAL;  in amdgpu_file_to_fpriv()
3041 	if (filp->f_op != &amdgpu_driver_kms_fops)  in amdgpu_file_to_fpriv()
3042 		return -EINVAL;  in amdgpu_file_to_fpriv()
3044 	file = filp->private_data;  in amdgpu_file_to_fpriv()
3045 	*fpriv = file->driver_priv;  in amdgpu_file_to_fpriv()
3144 	.driver.pm = pm_ptr(&amdgpu_pm_ops),