652 amdgpu_lookup_format_info(u32 format, uint64_t modifier)  in amdgpu_lookup_format_info()  argument
654 	if (!IS_AMD_FMT_MOD(modifier))  in amdgpu_lookup_format_info()
657 	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) < AMD_FMT_MOD_TILE_VER_GFX9 ||  in amdgpu_lookup_format_info()
658 	    AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12)  in amdgpu_lookup_format_info()
661 	if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))  in amdgpu_lookup_format_info()
666 	if (AMD_FMT_MOD_GET(DCC, modifier))  in amdgpu_lookup_format_info()
727 	u64 modifier = 0;  in convert_tiling_flags_to_modifier_gfx12()  local
731 		modifier = DRM_FORMAT_MOD_LINEAR;  in convert_tiling_flags_to_modifier_gfx12()
736 		modifier =  in convert_tiling_flags_to_modifier_gfx12()
744 	afb->base.modifier = modifier;  in convert_tiling_flags_to_modifier_gfx12()
752 	uint64_t modifier = 0;  in convert_tiling_flags_to_modifier()  local
760 		modifier = DRM_FORMAT_MOD_LINEAR;  in convert_tiling_flags_to_modifier()
856 		modifier = AMD_FMT_MOD |  in convert_tiling_flags_to_modifier()
881 			modifier |= AMD_FMT_MOD_SET(DCC, 1) |  in convert_tiling_flags_to_modifier()
906 				modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);  in convert_tiling_flags_to_modifier()
920 					modifier |= AMD_FMT_MOD_SET(RB, rb) |  in convert_tiling_flags_to_modifier()
930 								modifier);  in convert_tiling_flags_to_modifier()
938 	afb->base.modifier = modifier;  in convert_tiling_flags_to_modifier()
976 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned,  in get_dcc_block_size()  argument
979 	unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier);  in get_dcc_block_size()
988 		return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12);  in get_dcc_block_size()
993 		int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);  in get_dcc_block_size()
996 		    AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2)  in get_dcc_block_size()
1060 	uint64_t modifier = rfb->base.modifier;  in amdgpu_display_verify_sizes()  local
1068 		if (modifier == DRM_FORMAT_MOD_LINEAR) {  in amdgpu_display_verify_sizes()
1072 		} else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {  in amdgpu_display_verify_sizes()
1073 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);  in amdgpu_display_verify_sizes()
1097 			int swizzle = AMD_FMT_MOD_GET(TILE, modifier);  in amdgpu_display_verify_sizes()
1131 	if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&  in amdgpu_display_verify_sizes()
1132 	    AMD_FMT_MOD_GET(DCC, modifier)) {  in amdgpu_display_verify_sizes()
1133 		if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {  in amdgpu_display_verify_sizes()
1134 			block_size_log2 = get_dcc_block_size(modifier, false, false);  in amdgpu_display_verify_sizes()
1144 			block_size_log2 = get_dcc_block_size(modifier, true, true);  in amdgpu_display_verify_sizes()
1146 			bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier);  in amdgpu_display_verify_sizes()
1148 			block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned);  in amdgpu_display_verify_sizes()
1207 				      mode_cmd->modifier[0])) {  in amdgpu_display_gem_fb_verify_and_init()
1210 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);  in amdgpu_display_gem_fb_verify_and_init()