Lines Matching defs:afb

725 static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)
728 	int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
734 			AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
740 			AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) |
744 	afb->base.modifier = modifier;
745 	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
749 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
751 	struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
759 	if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
762 		int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
771 		uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
818 				if (!has_xor && afb->base.format->cpp[0] != 4)
857 			   AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
864 			bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
887 			afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
888 			afb->base.pitches[1] =
889 				AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
899 			if (extract_render_dcc_offset(adev, afb->base.obj[0],
902 			    render_dcc_offset != afb->base.offsets[1] &&
907 				afb->base.offsets[2] = render_dcc_offset;
925 				dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
926 				afb->base.pitches[2] = ALIGN(afb->base.width,
929 			format_info = amdgpu_lookup_format_info(afb->base.format->format,
934 			afb->base.format = format_info;
938 	afb->base.modifier = modifier;
939 	afb->base.flags |= DRM_MODE_FB_MODIFIERS;
944 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
948 	if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */
951 	micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
957 		drm_dbg_kms(afb->base.dev,