424 			adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;  in amdgpu_discovery_harvest_config_quirk()
425 			adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;  in amdgpu_discovery_harvest_config_quirk()
741 						adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;  in amdgpu_discovery_read_harvest_bit_per_ip()
742 						adev->vcn.inst_mask &=  in amdgpu_discovery_read_harvest_bit_per_ip()
747 						adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;  in amdgpu_discovery_read_harvest_bit_per_ip()
748 						adev->vcn.inst_mask &=  in amdgpu_discovery_read_harvest_bit_per_ip()
796 			adev->vcn.harvest_config |=  in amdgpu_discovery_read_from_harvest_table()
801 			adev->vcn.inst_mask &=  in amdgpu_discovery_read_from_harvest_table()
1094 			harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;  in amdgpu_discovery_get_harvest_info()
1410 	adev->vcn.inst_mask = 0;  in amdgpu_discovery_reg_base_init()
1459 				if (adev->vcn.num_vcn_inst <  in amdgpu_discovery_reg_base_init()
1461 					adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =  in amdgpu_discovery_reg_base_init()
1463 					adev->vcn.num_vcn_inst++;  in amdgpu_discovery_reg_base_init()
1464 					adev->vcn.inst_mask |=  in amdgpu_discovery_reg_base_init()
1470 						adev->vcn.num_vcn_inst + 1,  in amdgpu_discovery_reg_base_init()
1621 	if (vcn_harvest_count == adev->vcn.num_vcn_inst) {  in amdgpu_discovery_harvest_ip()
1824 	if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {  in amdgpu_discovery_get_vcn_info()
1842 		for (v = 0; v < adev->vcn.num_vcn_inst; v++) {  in amdgpu_discovery_get_vcn_info()
1843 			adev->vcn.inst[v].vcn_codec_disable_mask =  in amdgpu_discovery_get_vcn_info()
2750 		adev->vcn.num_vcn_inst = 1;  in amdgpu_discovery_set_ip_blocks()
2828 		adev->vcn.num_vcn_inst = 2;  in amdgpu_discovery_set_ip_blocks()
2863 		adev->vcn.num_vcn_inst = 2;  in amdgpu_discovery_set_ip_blocks()