143 					 struct cper_sec_crashdump_reg_data reg_data)  in amdgpu_cper_entry_fill_fatal_section()  argument
157 	section->body.reg_arr_size = sizeof(reg_data);  in amdgpu_cper_entry_fill_fatal_section()
158 	section->body.data = reg_data;  in amdgpu_cper_entry_fill_fatal_section()
293 	struct cper_sec_crashdump_reg_data reg_data = { 0 };  in amdgpu_cper_generate_ue_record()  local
303 	reg_data.status_lo = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);  in amdgpu_cper_generate_ue_record()
304 	reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);  in amdgpu_cper_generate_ue_record()
305 	reg_data.addr_lo   = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);  in amdgpu_cper_generate_ue_record()
306 	reg_data.addr_hi   = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);  in amdgpu_cper_generate_ue_record()
307 	reg_data.ipid_lo   = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);  in amdgpu_cper_generate_ue_record()
308 	reg_data.ipid_hi   = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);  in amdgpu_cper_generate_ue_record()
309 	reg_data.synd_lo   = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);  in amdgpu_cper_generate_ue_record()
310 	reg_data.synd_hi   = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);  in amdgpu_cper_generate_ue_record()
313 	ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data);  in amdgpu_cper_generate_ue_record()
371 	uint32_t reg_data[CPER_ACA_REG_COUNT] = { 0 };  in amdgpu_cper_generate_ce_records()  local
397 		reg_data[CPER_ACA_REG_CTL_LO]    = lower_32_bits(bank->regs[ACA_REG_IDX_CTL]);  in amdgpu_cper_generate_ce_records()
398 		reg_data[CPER_ACA_REG_CTL_HI]    = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]);  in amdgpu_cper_generate_ce_records()
399 		reg_data[CPER_ACA_REG_STATUS_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_STATUS]);  in amdgpu_cper_generate_ce_records()
400 		reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]);  in amdgpu_cper_generate_ce_records()
401 		reg_data[CPER_ACA_REG_ADDR_LO]   = lower_32_bits(bank->regs[ACA_REG_IDX_ADDR]);  in amdgpu_cper_generate_ce_records()
402 		reg_data[CPER_ACA_REG_ADDR_HI]   = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]);  in amdgpu_cper_generate_ce_records()
403 		reg_data[CPER_ACA_REG_MISC0_LO]  = lower_32_bits(bank->regs[ACA_REG_IDX_MISC0]);  in amdgpu_cper_generate_ce_records()
404 		reg_data[CPER_ACA_REG_MISC0_HI]  = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]);  in amdgpu_cper_generate_ce_records()
405 		reg_data[CPER_ACA_REG_CONFIG_LO] = lower_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);  in amdgpu_cper_generate_ce_records()
406 		reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]);  in amdgpu_cper_generate_ce_records()
407 		reg_data[CPER_ACA_REG_IPID_LO]   = lower_32_bits(bank->regs[ACA_REG_IDX_IPID]);  in amdgpu_cper_generate_ce_records()
408 		reg_data[CPER_ACA_REG_IPID_HI]   = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]);  in amdgpu_cper_generate_ce_records()
409 		reg_data[CPER_ACA_REG_SYND_LO]   = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);  in amdgpu_cper_generate_ce_records()
410 		reg_data[CPER_ACA_REG_SYND_HI]   = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);  in amdgpu_cper_generate_ce_records()
414 				reg_data, CPER_ACA_REG_COUNT);  in amdgpu_cper_generate_ce_records()