Lines Matching +full:gfx +full:- +full:mem
49 struct amdgpu_mode_info *mode_info = &adev->mode_info;
59 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
64 (mode_info->atom_context->bios + data_offset);
65 fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability);
83 fw_cap = adev->mode_info.firmware_flags;
94 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
97 (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
100 adev->bios_scratch_reg_offset =
101 le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
110 start_addr = le32_to_cpu(fw_usage->start_address_in_kb);
111 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
112 drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb);
122 /* Firmware request VRAM reservation for SR-IOV */
123 adev->mman.fw_vram_usage_start_offset = (start_addr &
125 adev->mman.fw_vram_usage_size = fw_size << 10;
139 fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb);
140 fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb);
142 drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb);
143 drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb);
154 /* Firmware request VRAM reservation for SR-IOV */
155 adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
157 adev->mman.fw_vram_usage_size = fw_size << 10;
163 /* driver request VRAM reservation for SR-IOV */
164 adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
166 adev->mman.drv_vram_usage_size = drv_size << 10;
175 struct atom_context *ctx = adev->mode_info.atom_context;
185 if (!(amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled)) {
189 (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
195 (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
203 ctx->scratch_size_bytes = 0;
207 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
208 if (!ctx->scratch)
209 return -ENOMEM;
210 ctx->scratch_size_bytes = usage_bytes;
248 if (adev->flags & AMD_IS_APU) {
304 struct amdgpu_mode_info *mode_info = &adev->mode_info;
318 if (adev->flags & AMD_IS_APU)
331 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
334 if (adev->flags & AMD_IS_APU) {
336 (mode_info->atom_context->bios + data_offset);
342 mem_channel_number = igp_info->v11.umachannelnumber;
345 mem_type = igp_info->v11.memorytype;
356 return -EINVAL;
363 mem_channel_number = igp_info->v21.umachannelnumber;
366 mem_type = igp_info->v21.memorytype;
377 mem_channel_number = igp_info->v23.umachannelnumber;
380 mem_type = igp_info->v23.memorytype;
391 return -EINVAL;
395 return -EINVAL;
401 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
406 mem_channel_number = le32_to_cpu(umc_info->v40.channel_num);
407 mem_type = le32_to_cpu(umc_info->v40.vram_type);
408 mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
409 mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
418 return -EINVAL;
421 return -EINVAL;
425 (mode_info->atom_context->bios + data_offset);
427 module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
432 vram_module = (union vram_module *)vram_info->v30.vram_module;
433 mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
436 mem_type = vram_info->v30.memory_type;
439 mem_channel_number = vram_info->v30.channel_num;
440 mem_channel_width = vram_info->v30.channel_width;
445 return -EINVAL;
451 if (module_id > vram_info->v23.vram_module_num)
453 vram_module = (union vram_module *)vram_info->v23.vram_module;
456 ((u8 *)vram_module + vram_module->v9.vram_module_size);
459 mem_type = vram_module->v9.memory_type;
462 mem_channel_number = vram_module->v9.channel_num;
463 mem_channel_width = vram_module->v9.channel_width;
466 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
472 if (module_id > vram_info->v24.vram_module_num)
474 vram_module = (union vram_module *)vram_info->v24.vram_module;
477 ((u8 *)vram_module + vram_module->v10.vram_module_size);
480 mem_type = vram_module->v10.memory_type;
483 mem_channel_number = vram_module->v10.channel_num;
484 mem_channel_width = vram_module->v10.channel_width;
487 mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
493 if (module_id > vram_info->v25.vram_module_num)
495 vram_module = (union vram_module *)vram_info->v25.vram_module;
498 ((u8 *)vram_module + vram_module->v11.vram_module_size);
501 mem_type = vram_module->v11.memory_type;
504 mem_channel_number = vram_module->v11.channel_num;
505 mem_channel_width = vram_module->v11.channel_width;
508 mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
514 if (module_id > vram_info->v26.vram_module_num)
516 vram_module = (union vram_module *)vram_info->v26.vram_module;
519 ((u8 *)vram_module + vram_module->v9.vram_module_size);
522 mem_type = vram_module->v9.memory_type;
525 mem_channel_number = vram_module->v9.channel_num;
526 mem_channel_width = vram_module->v9.channel_width;
529 mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
534 return -EINVAL;
538 return -EINVAL;
553 struct amdgpu_mode_info *mode_info = &adev->mode_info;
561 adev->ras_default_ecc_enabled = false;
566 if (amdgpu_atom_parse_data_header(mode_info->atom_context,
568 umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
572 umc_config = le32_to_cpu(umc_info->v31.umc_config);
577 umc_config = le32_to_cpu(umc_info->v32.umc_config);
582 umc_config = le32_to_cpu(umc_info->v33.umc_config);
583 umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
587 adev->ras_default_ecc_enabled =
597 umc_config = le32_to_cpu(umc_info->v40.umc_config);
598 umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
601 adev->ras_default_ecc_enabled =
628 fw_cap = adev->mode_info.firmware_flags;
644 fw_cap = adev->mode_info.firmware_flags;
650 * amdgpu_atomfirmware_ras_rom_addr -- Get the RAS EEPROM addr from VBIOS
662 struct amdgpu_mode_info *mode_info = &adev->mode_info;
671 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
677 (mode_info->atom_context->bios + data_offset);
679 * be a 19-bit EEPROM address, which would be
693 if (firmware_info->v34.ras_rom_i2c_slave_addr) {
695 *i2c_address = firmware_info->v34.ras_rom_i2c_slave_addr;
719 struct amdgpu_mode_info *mode_info = &adev->mode_info;
720 struct amdgpu_pll *spll = &adev->clock.spll;
721 struct amdgpu_pll *mpll = &adev->clock.mpll;
724 int ret = -EINVAL, index;
728 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
731 (union firmware_info *)(mode_info->atom_context->bios +
734 adev->clock.default_sclk =
735 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
736 adev->clock.default_mclk =
737 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
739 adev->pm.current_sclk = adev->clock.default_sclk;
740 adev->pm.current_mclk = adev->clock.default_mclk;
747 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
750 (union smu_info *)(mode_info->atom_context->bios +
755 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
757 spll->reference_freq = le32_to_cpu(smu_info->v40.core_refclk_10khz);
759 spll->reference_div = 0;
760 spll->min_post_div = 1;
761 spll->max_post_div = 1;
762 spll->min_ref_div = 2;
763 spll->max_ref_div = 0xff;
764 spll->min_feedback_div = 4;
765 spll->max_feedback_div = 0xff;
766 spll->best_vco = 0;
773 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
776 (union umc_info *)(mode_info->atom_context->bios +
780 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
782 mpll->reference_div = 0;
783 mpll->min_post_div = 1;
784 mpll->max_post_div = 1;
785 mpll->min_ref_div = 2;
786 mpll->max_ref_div = 0xff;
787 mpll->min_feedback_div = 4;
788 mpll->max_feedback_div = 0xff;
789 mpll->best_vco = 0;
796 if (adev->asic_type >= CHIP_NAVI10) {
799 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
802 (mode_info->atom_context->bios + data_offset);
805 spll->reference_freq = le32_to_cpu(gfx_info->v30.golden_tsc_count_lower_refclk);
810 spll->reference_freq = le32_to_cpu(gfx_info->v22.rlc_gpu_timer_refclk);
823 struct amdgpu_mode_info *mode_info = &adev->mode_info;
830 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
833 (mode_info->atom_context->bios + data_offset);
837 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
838 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
839 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
840 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
841 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
842 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
843 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
844 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
845 adev->gfx.config.gs_prim_buffer_depth =
846 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
847 adev->gfx.config.double_offchip_lds_buf =
848 gfx_info->v24.gc_double_offchip_lds_buffer;
849 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
850 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
851 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
852 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
855 adev->gfx.config.max_shader_engines = gfx_info->v27.max_shader_engines;
856 adev->gfx.config.max_cu_per_sh = gfx_info->v27.max_cu_per_sh;
857 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se;
858 adev->gfx.config.max_backends_per_se = gfx_info->v27.max_backends_per_se;
859 adev->gfx.config.max_texture_channel_caches = gfx_info->v27.max_texture_channel_caches;
860 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v27.gc_num_gprs);
861 adev->gfx.config.max_gs_threads = gfx_info->v27.gc_num_max_gs_thds;
862 adev->gfx.config.gs_vgt_table_depth = gfx_info->v27.gc_gs_table_depth;
863 adev->gfx.config.gs_prim_buffer_depth = le16_to_cpu(gfx_info->v27.gc_gsprim_buff_depth);
864 adev->gfx.config.double_offchip_lds_buf = gfx_info->v27.gc_double_offchip_lds_buffer;
865 adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v27.gc_wave_size);
866 adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v27.gc_max_waves_per_simd);
867 adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v27.gc_max_scratch_slots_per_cu;
868 adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v27.gc_lds_size);
871 return -EINVAL;
876 adev->gfx.config.max_shader_engines = gfx_info->v30.max_shader_engines;
877 adev->gfx.config.max_cu_per_sh = gfx_info->v30.max_cu_per_sh;
878 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se;
879 adev->gfx.config.max_backends_per_se = gfx_info->v30.max_backends_per_se;
880 adev->gfx.config.max_texture_channel_caches = gfx_info->v30.max_texture_channel_caches;
883 return -EINVAL;
886 return -EINVAL;
890 return -EINVAL;
894 * Helper function to query two stage mem training capability
898 * Return true if two stage mem training is supported or false if not
904 fw_cap = adev->mode_info.firmware_flags;
911 struct atom_context *ctx = adev->mode_info.atom_context;
926 firmware_info = (union firmware_info *)(ctx->bios + data_offset);
929 return -EINVAL;
934 (firmware_info->v34.fw_reserved_size_in_kb << 10);
938 (firmware_info->v35.fw_reserved_size_in_kb << 10);
958 struct amdgpu_mode_info *mode_info = &adev->mode_info;
967 return -EINVAL;
969 ctx = mode_info->atom_context;
971 return -EINVAL;
979 (union firmware_info *)(ctx->bios +
983 le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
985 le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
987 return -EINVAL;
992 if (amdgpu_atom_parse_cmd_header(mode_info->atom_context, index, &frev, &crev)) {
1003 return -EINVAL;
1006 return -EINVAL;