Lines Matching defs:adev
70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
72 bool vf = amdgpu_sriov_vf(adev);
77 adev->kfd.dev = kgd2kfd_probe(adev, vf);
84 * @adev: amdgpu_device pointer
93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
102 if (adev->enable_mes) {
109 *aperture_base = adev->doorbell.base;
112 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells *
114 *aperture_base = adev->doorbell.base;
115 *aperture_size = adev->doorbell.size;
116 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);
127 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
135 reset_context.reset_req_dev = adev;
136 reset_context.src = adev->enable_mes ?
141 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
148 int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev)
152 if (!adev->kfd.init_complete || adev->kfd.client.dev)
155 ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd",
158 dev_err(adev->dev, "Failed to init DRM client: %d\n",
163 drm_client_register(&adev->kfd.client);
168 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
175 if (adev->kfd.dev) {
179 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
180 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
181 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
182 .gpuvm_size = min(adev->vm_manager.max_pfn
185 .drm_render_minor = adev_to_drm(adev)->render->index,
186 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
187 .enable_mes = adev->enable_mes,
194 adev->gfx.mec_bitmap[0].queue_bitmap,
201 * adev->gfx.mec.num_pipe_per_mec
202 * adev->gfx.mec.num_queue_per_pipe;
206 amdgpu_doorbell_get_kfd_info(adev,
219 if (adev->asic_type >= CHIP_VEGA10) {
221 adev->doorbell_index.first_non_cp;
223 adev->doorbell_index.last_non_cp;
226 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
229 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
231 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
235 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
237 if (adev->kfd.dev) {
238 kgd2kfd_device_exit(adev->kfd.dev);
239 adev->kfd.dev = NULL;
240 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size;
244 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
247 if (adev->kfd.dev)
248 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
251 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
253 if (adev->kfd.dev)
254 kgd2kfd_suspend(adev->kfd.dev, run_pm);
257 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
261 if (adev->kfd.dev)
262 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
267 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
272 if (adev->kfd.dev)
273 r = kgd2kfd_pre_reset(adev->kfd.dev, reset_context);
278 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
282 if (adev->kfd.dev)
283 r = kgd2kfd_post_reset(adev->kfd.dev);
288 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
290 if (amdgpu_device_should_recover_gpu(adev))
291 amdgpu_reset_domain_schedule(adev->reset_domain,
292 &adev->kfd.reset_work);
295 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
316 r = amdgpu_bo_create(adev, &bp, &bo);
318 dev_err(adev->dev,
326 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
332 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
338 dev_err(adev->dev, "%p bind failed\n", bo);
344 dev_err(adev->dev,
367 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj)
378 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
395 r = amdgpu_bo_create_user(adev, &bp, &ubo);
397 dev_err(adev->dev,
407 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
414 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
419 return adev->gfx.pfp_fw_version;
422 return adev->gfx.me_fw_version;
425 return adev->gfx.ce_fw_version;
428 return adev->gfx.mec_fw_version;
431 return adev->gfx.mec2_fw_version;
434 return adev->gfx.rlc_fw_version;
437 return adev->sdma.instance[0].fw_version;
440 return adev->sdma.instance[1].fw_version;
449 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
456 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size)
458 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
461 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
462 } else if (adev->apu_prefer_gtt) {
466 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
467 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
468 adev->gmc.visible_vram_size;
470 mem_info->vram_width = adev->gmc.vram_width;
473 &adev->gmc.aper_base,
477 if (adev->pm.dpm_enabled) {
481 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
486 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
488 if (adev->gfx.funcs->get_gpu_clock_counter)
489 return adev->gfx.funcs->get_gpu_clock_counter(adev);
493 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
496 if (adev->pm.dpm_enabled)
497 return amdgpu_dpm_get_sclk(adev, false) / 100;
502 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
523 if (obj->dev->driver != adev_to_drm(adev)->driver)
527 adev = drm_to_adev(obj->dev);
536 *dmabuf_adev = adev;
558 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
560 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
561 fls(adev->pm.pcie_mlw_mask)) - 1;
562 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
564 fls(adev->pm.pcie_gen_mask &
615 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
628 ring = &adev->gfx.compute_ring[0];
631 ring = &adev->sdma.instance[0].ring;
634 ring = &adev->sdma.instance[1].ring;
642 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job);
673 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
676 if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
677 ((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) ||
678 (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {
680 amdgpu_gfx_off_ctrl(adev, idle);
681 } else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &&
682 (adev->flags & AMD_IS_APU)) {
686 struct amdgpu_ip_block *gfx_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
690 amdgpu_dpm_switch_power_profile(adev,
695 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
697 if (adev->kfd.dev)
698 return vmid >= adev->vm_manager.first_kfd_vmid;
703 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
705 return adev->have_atomics_support;
708 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
710 amdgpu_device_flush_hdp(adev, NULL);
713 bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev)
715 return amdgpu_ras_get_fed_status(adev);
718 void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,
722 amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset);
725 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
728 amdgpu_umc_pasid_poison_handler(adev, block, 0, NULL, NULL, reset);
731 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
737 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih);
742 amdgpu_amdkfd_interrupt(adev, payload);
747 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)
752 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)
758 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
760 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id);
763 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
764 if (adev->gmc.is_app_apu && adev->gmc.num_mem_partitions == 1) {
775 tmp = adev->gmc.mem_partitions[mem_id].size;
777 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
779 } else if (adev->apu_prefer_gtt) {
782 return adev->gmc.real_vram_size;
786 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
789 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
798 if (!kiq_ring->sched.ready || amdgpu_in_reset(adev))
846 int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id)
848 if (!adev->kfd.init_complete)
851 return kgd2kfd_stop_sched(adev->kfd.dev, node_id);
855 int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id)
857 if (!adev->kfd.init_complete)
860 return kgd2kfd_start_sched(adev->kfd.dev, node_id);
864 bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id)
866 if (!adev->kfd.init_complete)
869 return kgd2kfd_compute_active(adev->kfd.dev, node_id);
873 int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,
878 if (!adev->kfd.init_complete)
881 r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable,