Lines Matching defs:and

7  * copy of this software and associated documentation files (the "Software"),
10  * and/or sell copies of the Software, and to permit persons to whom the
13  * The above copyright notice and this permission notice shall be included in
283 #define AMDGPU_VBIOS_VGA_ALLOCATION		(9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
475  * components had some level of writeback memory, and this struct initially
492 	 * For the GPU address, it is necessary to use gpu_addr and the offset.
520 	 * Protects read and write of the used field array.
545  * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
556  * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
560  *                 and does a secondary bus reset or FLR, depending on what the
681  * Core structure, functions and helpers.
984 	/* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
1064 	/* for userq and VM fences */
1121 	/* soc15 register offset based on ip, instance and  segment */
1244  * as fence address and writes a 32 bit fence value to this address.
1246  * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety.
1253 	/* This considers only major/minor/rev and ignores
1404 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)