22 #define ADP_INT_STATUS 0x34
23 #define ADP_INT_STATUS_INT_MASK 0x7
24 #define ADP_INT_STATUS_VBLANK 0x1
25 #define ADP_CTRL 0x100
26 #define ADP_CTRL_VBLANK_ON 0x12
27 #define ADP_CTRL_FIFO_ON 0x601
28 #define ADP_SCREEN_SIZE 0x0c
29 #define ADP_SCREEN_HSIZE GENMASK(15, 0)
32 #define ADBE_FIFO 0x10c0
33 #define ADBE_FIFO_SYNC 0xc0000000
35 #define ADBE_BLEND_BYPASS 0x2020
36 #define ADBE_BLEND_EN1 0x2028
37 #define ADBE_BLEND_EN2 0x2074
38 #define ADBE_BLEND_EN3 0x202c
39 #define ADBE_BLEND_EN4 0x2034
40 #define ADBE_MASK_BUF 0x2200
42 #define ADBE_SRC_START 0x4040
43 #define ADBE_SRC_SIZE 0x4048
44 #define ADBE_DST_START 0x4050
45 #define ADBE_DST_SIZE 0x4054
46 #define ADBE_STRIDE 0x4038
47 #define ADBE_FB_BASE 0x4030
49 #define ADBE_LAYER_EN1 0x4020
50 #define ADBE_LAYER_EN2 0x4068
51 #define ADBE_LAYER_EN3 0x40b4
52 #define ADBE_LAYER_EN4 0x40f4
53 #define ADBE_SCALE_CTL 0x40ac
54 #define ADBE_SCALE_CTL_BYPASS 0x100000
56 #define ADBE_LAYER_CTL 0x1038
57 #define ADBE_LAYER_CTL_ENABLE 0x10000
59 #define ADBE_PIX_FMT 0x402c
60 #define ADBE_PIX_FMT_XRGB32 0x53e4001
71 	if (current->comm[0] == 'X')  in adp_open()
107 	.major = 0,
139 		return 0;  in adp_plane_atomic_check()
180 	writel(fb->pitches[0], adp->be + ADBE_STRIDE);  in adp_plane_atomic_update()
181 	obj = drm_fb_dma_get_gem_obj(fb, 0);  in adp_plane_atomic_update()
183 		writel(obj->dma_addr + fb->offsets[0], adp->be + ADBE_FB_BASE);  in adp_plane_atomic_update()
185 	writel(BIT(0), adp->be + ADBE_LAYER_EN1);  in adp_plane_atomic_update()
186 	writel(BIT(0), adp->be + ADBE_LAYER_EN2);  in adp_plane_atomic_update()
187 	writel(BIT(0), adp->be + ADBE_LAYER_EN3);  in adp_plane_atomic_update()
188 	writel(BIT(0), adp->be + ADBE_LAYER_EN4);  in adp_plane_atomic_update()
190 	writel(ADBE_LAYER_CTL_ENABLE | BIT(0), adp->be + ADBE_LAYER_CTL);  in adp_plane_atomic_update()
199 	writel(0x0, adp->be + ADBE_LAYER_EN1);  in adp_plane_atomic_disable()
200 	writel(0x0, adp->be + ADBE_LAYER_EN2);  in adp_plane_atomic_disable()
201 	writel(0x0, adp->be + ADBE_LAYER_EN3);  in adp_plane_atomic_disable()
202 	writel(0x0, adp->be + ADBE_LAYER_EN4);  in adp_plane_atomic_disable()
230 	plane = __drmm_universal_plane_alloc(drm, sizeof(struct drm_plane), 0,  in adp_plane_new()
260 	return 0;  in adp_crtc_enable_vblank()
285 	writel(BIT(0), adp->be + ADBE_BLEND_EN2);  in adp_crtc_atomic_enable()
287 	writel(BIT(0), adp->be + ADBE_BLEND_EN3);  in adp_crtc_atomic_enable()
288 	writel(BIT(0), adp->be + ADBE_BLEND_BYPASS);  in adp_crtc_atomic_enable()
289 	writel(BIT(0), adp->be + ADBE_BLEND_EN4);  in adp_crtc_atomic_enable()
301 	writel(0x0, adp->be + ADBE_BLEND_EN2);  in adp_crtc_atomic_disable()
302 	writel(0x0, adp->be + ADBE_BLEND_EN1);  in adp_crtc_atomic_disable()
303 	writel(0x0, adp->be + ADBE_BLEND_EN3);  in adp_crtc_atomic_disable()
304 	writel(0x0, adp->be + ADBE_BLEND_BYPASS);  in adp_crtc_atomic_disable()
305 	writel(0x0, adp->be + ADBE_BLEND_EN4);  in adp_crtc_atomic_disable()
324 		if (new_size != 0) {  in adp_crtc_atomic_flush()
327 			memset(adp->mask_buf, 0xFF, new_size);  in adp_crtc_atomic_flush()
340 		if (drm_crtc_vblank_get(crtc) != 0)  in adp_crtc_atomic_flush()
383 	return 0;  in adp_setup_crtc()
419 	drm->mode_config.prefer_shadow = 0;  in adp_setup_mode_config()
449 	if (ret < 0) {  in adp_setup_mode_config()
456 	return 0;  in adp_setup_mode_config()
476 	if (adp->be_irq < 0)  in adp_parse_of()
480 	if (adp->fe_irq < 0)  in adp_parse_of()
483 	return 0;  in adp_parse_of()
498 			if ((int_ctl & 0xF00) == 0x600) {  in adp_fe_irq()
521 	adp->next_bridge = drmm_of_get_bridge(&adp->drm, dev->of_node, 0, 0);  in adp_drm_bind()
528 	if (err < 0)  in adp_drm_bind()
531 	err = request_irq(adp->fe_irq, adp_fe_irq, 0, "adp-fe", adp);  in adp_drm_bind()
535 	err = drm_dev_register(&adp->drm, 0);  in adp_drm_bind()
539 	return 0;  in adp_drm_bind()
576 	if (err < 0)  in adp_probe()
579 	port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);  in adp_probe()