163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)  in zynq_gpio_is_zynq()  argument
165 	return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);  in zynq_gpio_is_zynq()
174 static int gpio_data_ro_bug(struct zynq_gpio *gpio)  in gpio_data_ro_bug()  argument
176 	return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);  in gpio_data_ro_bug()
194 					  struct zynq_gpio *gpio)  in zynq_gpio_get_bank_pin()  argument
198 	for (bank = 0; bank < gpio->p_data->max_bank; bank++) {  in zynq_gpio_get_bank_pin()
199 		if ((pin_num >= gpio->p_data->bank_min[bank]) &&  in zynq_gpio_get_bank_pin()
200 		    (pin_num <= gpio->p_data->bank_max[bank])) {  in zynq_gpio_get_bank_pin()
203 					gpio->p_data->bank_min[bank];  in zynq_gpio_get_bank_pin()
206 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_get_bank_pin()
229 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_get_value()  local
231 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_get_value()
233 	if (gpio_data_ro_bug(gpio)) {  in zynq_gpio_get_value()
234 		if (zynq_gpio_is_zynq(gpio)) {  in zynq_gpio_get_value()
236 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
239 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
244 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
247 				data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
252 		data = readl_relaxed(gpio->base_addr +  in zynq_gpio_get_value()
272 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_set_value()  local
274 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_value()
292 	writel_relaxed(state, gpio->base_addr + reg_offset);  in zynq_gpio_set_value()
310 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_dir_in()  local
312 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_in()
318 	if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&  in zynq_gpio_dir_in()
323 	spin_lock_irqsave(&gpio->dirlock, flags);  in zynq_gpio_dir_in()
324 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
326 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_in()
327 	spin_unlock_irqrestore(&gpio->dirlock, flags);  in zynq_gpio_dir_in()
350 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_dir_out()  local
352 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_dir_out()
355 	spin_lock_irqsave(&gpio->dirlock, flags);  in zynq_gpio_dir_out()
356 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
358 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_dir_out()
361 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
363 	writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));  in zynq_gpio_dir_out()
364 	spin_unlock_irqrestore(&gpio->dirlock, flags);  in zynq_gpio_dir_out()
384 	struct zynq_gpio *gpio = gpiochip_get_data(chip);  in zynq_gpio_get_direction()  local
386 	zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_get_direction()
388 	reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));  in zynq_gpio_get_direction()
409 	struct zynq_gpio *gpio =  in zynq_gpio_irq_mask()  local
414 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_mask()
416 		       gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));  in zynq_gpio_irq_mask()
433 	struct zynq_gpio *gpio =  in zynq_gpio_irq_unmask()  local
438 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_unmask()
440 		       gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));  in zynq_gpio_irq_unmask()
454 	struct zynq_gpio *gpio =  in zynq_gpio_irq_ack()  local
458 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_irq_ack()
460 		       gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));  in zynq_gpio_irq_ack()
505 	struct zynq_gpio *gpio =  in zynq_gpio_set_irq_type()  local
509 	zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);  in zynq_gpio_set_irq_type()
511 	int_type = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
513 	int_pol = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
515 	int_any = readl_relaxed(gpio->base_addr +  in zynq_gpio_set_irq_type()
550 		       gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
552 		       gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
554 		       gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));  in zynq_gpio_set_irq_type()
570 	struct zynq_gpio *gpio =  in zynq_gpio_set_wake()  local
573 	irq_set_irq_wake(gpio->irq, on);  in zynq_gpio_set_wake()
626 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,  in zynq_gpio_handle_bank_irq()  argument
630 	unsigned int bank_offset = gpio->p_data->bank_min[bank_num];  in zynq_gpio_handle_bank_irq()
631 	struct irq_domain *irqdomain = gpio->chip.irq.domain;  in zynq_gpio_handle_bank_irq()
655 	struct zynq_gpio *gpio =  in zynq_gpio_irqhandler()  local
661 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_irqhandler()
662 		int_sts = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
664 		int_enb = readl_relaxed(gpio->base_addr +  in zynq_gpio_irqhandler()
666 		zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);  in zynq_gpio_irqhandler()
667 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_irqhandler()
674 static void zynq_gpio_save_context(struct zynq_gpio *gpio)  in zynq_gpio_save_context()  argument
678 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_save_context()
679 		gpio->context.datalsw[bank_num] =  in zynq_gpio_save_context()
680 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
682 		gpio->context.datamsw[bank_num] =  in zynq_gpio_save_context()
683 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
685 		gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
687 		gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
689 		gpio->context.int_type[bank_num] =  in zynq_gpio_save_context()
690 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
692 		gpio->context.int_polarity[bank_num] =  in zynq_gpio_save_context()
693 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
695 		gpio->context.int_any[bank_num] =  in zynq_gpio_save_context()
696 				readl_relaxed(gpio->base_addr +  in zynq_gpio_save_context()
698 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_save_context()
703 static void zynq_gpio_restore_context(struct zynq_gpio *gpio)  in zynq_gpio_restore_context()  argument
707 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_restore_context()
708 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_restore_context()
710 		writel_relaxed(gpio->context.datalsw[bank_num],  in zynq_gpio_restore_context()
711 			       gpio->base_addr +  in zynq_gpio_restore_context()
713 		writel_relaxed(gpio->context.datamsw[bank_num],  in zynq_gpio_restore_context()
714 			       gpio->base_addr +  in zynq_gpio_restore_context()
716 		writel_relaxed(gpio->context.dirm[bank_num],  in zynq_gpio_restore_context()
717 			       gpio->base_addr +  in zynq_gpio_restore_context()
719 		writel_relaxed(gpio->context.int_type[bank_num],  in zynq_gpio_restore_context()
720 			       gpio->base_addr +  in zynq_gpio_restore_context()
722 		writel_relaxed(gpio->context.int_polarity[bank_num],  in zynq_gpio_restore_context()
723 			       gpio->base_addr +  in zynq_gpio_restore_context()
725 		writel_relaxed(gpio->context.int_any[bank_num],  in zynq_gpio_restore_context()
726 			       gpio->base_addr +  in zynq_gpio_restore_context()
728 		writel_relaxed(~(gpio->context.int_en[bank_num]),  in zynq_gpio_restore_context()
729 			       gpio->base_addr +  in zynq_gpio_restore_context()
731 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_restore_context()
738 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_suspend()  local
739 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_suspend()
747 		disable_irq(gpio->irq);  in zynq_gpio_suspend()
750 		zynq_gpio_save_context(gpio);  in zynq_gpio_suspend()
759 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_resume()  local
760 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in zynq_gpio_resume()
769 		enable_irq(gpio->irq);  in zynq_gpio_resume()
773 		zynq_gpio_restore_context(gpio);  in zynq_gpio_resume()
782 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_runtime_suspend()  local
784 	clk_disable_unprepare(gpio->clk);  in zynq_gpio_runtime_suspend()
791 	struct zynq_gpio *gpio = dev_get_drvdata(dev);  in zynq_gpio_runtime_resume()  local
793 	return clk_prepare_enable(gpio->clk);  in zynq_gpio_runtime_resume()
902 	struct zynq_gpio *gpio;  in zynq_gpio_probe()  local
907 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in zynq_gpio_probe()
908 	if (!gpio)  in zynq_gpio_probe()
916 	gpio->p_data = match->data;  in zynq_gpio_probe()
917 	platform_set_drvdata(pdev, gpio);  in zynq_gpio_probe()
919 	gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);  in zynq_gpio_probe()
920 	if (IS_ERR(gpio->base_addr))  in zynq_gpio_probe()
921 		return PTR_ERR(gpio->base_addr);  in zynq_gpio_probe()
923 	gpio->irq = platform_get_irq(pdev, 0);  in zynq_gpio_probe()
924 	if (gpio->irq < 0)  in zynq_gpio_probe()
925 		return gpio->irq;  in zynq_gpio_probe()
928 	chip = &gpio->chip;  in zynq_gpio_probe()
929 	chip->label = gpio->p_data->label;  in zynq_gpio_probe()
940 	chip->ngpio = gpio->p_data->ngpio;  in zynq_gpio_probe()
943 	gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in zynq_gpio_probe()
944 	if (IS_ERR(gpio->clk))  in zynq_gpio_probe()
945 		return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");  in zynq_gpio_probe()
947 	spin_lock_init(&gpio->dirlock);  in zynq_gpio_probe()
956 	for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {  in zynq_gpio_probe()
957 		writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +  in zynq_gpio_probe()
959 		if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)  in zynq_gpio_probe()
975 	girq->parents[0] = gpio->irq;  in zynq_gpio_probe()
980 	ret = gpiochip_add_data(chip, gpio);  in zynq_gpio_probe()
986 	irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);  in zynq_gpio_probe()
1008 	struct zynq_gpio *gpio = platform_get_drvdata(pdev);  in zynq_gpio_remove()  local
1014 	gpiochip_remove(&gpio->chip);  in zynq_gpio_remove()