Lines Matching +full:gpio +full:- +full:pin +full:- +full:interrupt
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
63 /* Register offsets for the GPIO device */
64 /* LSW Mask & Data -WO */
66 /* MSW Mask & Data -WO */
68 /* Data Register-RW */
71 /* Direction mode reg-RW */
73 /* Output enable reg-RW */
75 /* Interrupt mask reg-RO */
77 /* Interrupt enable reg-WO */
79 /* Interrupt disable reg-WO */
81 /* Interrupt status reg-RO */
83 /* Interrupt type reg-RW */
85 /* Interrupt polarity reg-RW */
87 /* Interrupt on any, reg-RW */
93 /* Mid pin number of a bank */
96 /* GPIO upper 16 bit mask */
117 * struct zynq_gpio - gpio device private data structure
119 * @base_addr: base address of the GPIO device
121 * @irq: interrupt for the GPIO device
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
159 * @gpio: Pointer to driver data struct
163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) in zynq_gpio_is_zynq() argument
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); in zynq_gpio_is_zynq()
169 * gpio_data_ro_bug - test if HW bug exists or not
170 * @gpio: Pointer to driver data struct
174 static int gpio_data_ro_bug(struct zynq_gpio *gpio) in gpio_data_ro_bug() argument
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); in gpio_data_ro_bug()
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
184 * pin
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
187 * @gpio: gpio device data structure
189 * Returns the bank number and pin offset within the bank.
194 struct zynq_gpio *gpio) in zynq_gpio_get_bank_pin() argument
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
199 if ((pin_num >= gpio->p_data->bank_min[bank]) && in zynq_gpio_get_bank_pin()
200 (pin_num <= gpio->p_data->bank_max[bank])) { in zynq_gpio_get_bank_pin()
202 *bank_pin_num = pin_num - in zynq_gpio_get_bank_pin()
203 gpio->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_get_bank_pin()
211 WARN(true, "invalid GPIO pin number: %u", pin_num); in zynq_gpio_get_bank_pin()
217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
219 * @pin: gpio pin number within the device
221 * This function reads the state of the specified pin of the GPIO device.
223 * Return: 0 if the pin is low, 1 if pin is high.
225 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) in zynq_gpio_get_value() argument
229 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_get_value() local
231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_value()
233 if (gpio_data_ro_bug(gpio)) { in zynq_gpio_get_value()
234 if (zynq_gpio_is_zynq(gpio)) { in zynq_gpio_get_value()
236 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
244 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
252 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
259 * zynq_gpio_set_value - Modify the state of the pin with specified value
261 * @pin: gpio pin number within the device
262 * @state: value used to modify the state of the specified pin
265 * upper 16 bits) based on the given pin number and sets the state of a
266 * gpio pin to the specified value. The state is either 0 or non-zero.
268 static int zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, in zynq_gpio_set_value() argument
272 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_set_value() local
274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_value()
278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; in zynq_gpio_set_value()
292 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
298 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
300 * @pin: gpio pin number within the device
302 * This function uses the read-modify-write sequence to set the direction of
303 * the gpio pin as input.
307 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) in zynq_gpio_dir_in() argument
312 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_in() local
314 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_in()
320 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && in zynq_gpio_dir_in()
322 return -EINVAL; in zynq_gpio_dir_in()
324 /* clear the bit in direction mode reg to set the pin as input */ in zynq_gpio_dir_in()
325 spin_lock_irqsave(&gpio->dirlock, flags); in zynq_gpio_dir_in()
326 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
328 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
329 spin_unlock_irqrestore(&gpio->dirlock, flags); in zynq_gpio_dir_in()
335 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
337 * @pin: gpio pin number within the device
338 * @state: value to be written to specified pin
340 * This function sets the direction of specified GPIO pin as output, configures
341 * the Output Enable register for the pin and uses zynq_gpio_set to set
342 * the state of the pin to the value specified.
346 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, in zynq_gpio_dir_out() argument
352 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_dir_out() local
354 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_dir_out()
356 /* set the GPIO pin as output */ in zynq_gpio_dir_out()
357 spin_lock_irqsave(&gpio->dirlock, flags); in zynq_gpio_dir_out()
358 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
360 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
362 /* configure the output enable reg for the pin */ in zynq_gpio_dir_out()
363 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
365 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
366 spin_unlock_irqrestore(&gpio->dirlock, flags); in zynq_gpio_dir_out()
368 /* set the state of the pin */ in zynq_gpio_dir_out()
369 zynq_gpio_set_value(chip, pin, state); in zynq_gpio_dir_out()
374 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
376 * @pin: gpio pin number within the device
378 * This function returns the direction of the specified GPIO.
382 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) in zynq_gpio_get_direction() argument
386 struct zynq_gpio *gpio = gpiochip_get_data(chip); in zynq_gpio_get_direction() local
388 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); in zynq_gpio_get_direction()
390 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_direction()
399 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
402 * This function calculates gpio pin number from irq number and sets the
403 * bit in the Interrupt Disable register of the corresponding bank to disable
404 * interrupts for that pin.
411 struct zynq_gpio *gpio = in zynq_gpio_irq_mask() local
415 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_mask()
416 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_mask()
418 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); in zynq_gpio_irq_mask()
422 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
423 * @irq_data: irq data containing irq number of gpio pin for the interrupt
426 * This function calculates the gpio pin number from irq number and sets the
427 * bit in the Interrupt Enable register of the corresponding bank to enable
428 * interrupts for that pin.
435 struct zynq_gpio *gpio = in zynq_gpio_irq_unmask() local
439 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_unmask()
440 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_unmask()
442 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); in zynq_gpio_irq_unmask()
446 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
447 * @irq_data: irq data containing irq number of gpio pin for the interrupt
450 * This function calculates gpio pin number from irq number and sets the bit
451 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
456 struct zynq_gpio *gpio = in zynq_gpio_irq_ack() local
459 device_pin_num = irq_data->hwirq; in zynq_gpio_irq_ack()
460 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_irq_ack()
462 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); in zynq_gpio_irq_ack()
466 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
467 * @irq_data: irq data containing irq number of gpio pin for the interrupt
470 * Clears the INTSTS bit and unmasks the given interrupt.
475 * The Zynq GPIO controller does not disable interrupt detection when in zynq_gpio_irq_enable()
476 * the interrupt is masked and only disables the propagation of the in zynq_gpio_irq_enable()
477 * interrupt. This means when the controller detects an interrupt in zynq_gpio_irq_enable()
478 * condition while the interrupt is logically disabled it will propagate in zynq_gpio_irq_enable()
479 * that interrupt event once the interrupt is enabled. This will cause in zynq_gpio_irq_enable()
480 * the interrupt consumer to see spurious interrupts to prevent this in zynq_gpio_irq_enable()
481 * first make sure that the interrupt is not asserted and then enable in zynq_gpio_irq_enable()
489 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
490 * @irq_data: irq data containing irq number of gpio pin
491 * @type: interrupt type that is to be set for the gpio pin
493 * This function gets the gpio pin number and its bank from the gpio pin number
497 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
498 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
499 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
500 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
501 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
507 struct zynq_gpio *gpio = in zynq_gpio_set_irq_type() local
510 device_pin_num = irq_data->hwirq; in zynq_gpio_set_irq_type()
511 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); in zynq_gpio_set_irq_type()
513 int_type = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
515 int_pol = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
517 int_any = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
548 return -EINVAL; in zynq_gpio_set_irq_type()
552 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
554 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
556 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); in zynq_gpio_set_irq_type()
572 struct zynq_gpio *gpio = in zynq_gpio_set_wake() local
575 irq_set_irq_wake(gpio->irq, on); in zynq_gpio_set_wake()
585 ret = pm_runtime_resume_and_get(chip->parent); in zynq_gpio_irq_reqres()
589 return gpiochip_reqres_irq(chip, d->hwirq); in zynq_gpio_irq_reqres()
596 gpiochip_relres_irq(chip, d->hwirq); in zynq_gpio_irq_relres()
597 pm_runtime_put(chip->parent); in zynq_gpio_irq_relres()
628 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, in zynq_gpio_handle_bank_irq() argument
632 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; in zynq_gpio_handle_bank_irq()
633 struct irq_domain *irqdomain = gpio->chip.irq.domain; in zynq_gpio_handle_bank_irq()
644 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
647 * This function reads the Interrupt Status Register of each bank to get the
648 * gpio pin number which has triggered an interrupt. It then acks the triggered
649 * interrupt and calls the pin specific handler set by the higher layer
650 * application for that pin.
651 * Note: A bug is reported if no handler is set for the gpio pin.
657 struct zynq_gpio *gpio = in zynq_gpio_irqhandler() local
663 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_irqhandler()
664 int_sts = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
666 int_enb = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
668 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); in zynq_gpio_irqhandler()
669 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_irqhandler()
676 static void zynq_gpio_save_context(struct zynq_gpio *gpio) in zynq_gpio_save_context() argument
680 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_save_context()
681 gpio->context.datalsw[bank_num] = in zynq_gpio_save_context()
682 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
684 gpio->context.datamsw[bank_num] = in zynq_gpio_save_context()
685 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
687 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
689 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
691 gpio->context.int_type[bank_num] = in zynq_gpio_save_context()
692 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
694 gpio->context.int_polarity[bank_num] = in zynq_gpio_save_context()
695 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
697 gpio->context.int_any[bank_num] = in zynq_gpio_save_context()
698 readl_relaxed(gpio->base_addr + in zynq_gpio_save_context()
700 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_save_context()
705 static void zynq_gpio_restore_context(struct zynq_gpio *gpio) in zynq_gpio_restore_context() argument
709 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_restore_context()
710 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_restore_context()
712 writel_relaxed(gpio->context.datalsw[bank_num], in zynq_gpio_restore_context()
713 gpio->base_addr + in zynq_gpio_restore_context()
715 writel_relaxed(gpio->context.datamsw[bank_num], in zynq_gpio_restore_context()
716 gpio->base_addr + in zynq_gpio_restore_context()
718 writel_relaxed(gpio->context.dirm[bank_num], in zynq_gpio_restore_context()
719 gpio->base_addr + in zynq_gpio_restore_context()
721 writel_relaxed(gpio->context.int_type[bank_num], in zynq_gpio_restore_context()
722 gpio->base_addr + in zynq_gpio_restore_context()
724 writel_relaxed(gpio->context.int_polarity[bank_num], in zynq_gpio_restore_context()
725 gpio->base_addr + in zynq_gpio_restore_context()
727 writel_relaxed(gpio->context.int_any[bank_num], in zynq_gpio_restore_context()
728 gpio->base_addr + in zynq_gpio_restore_context()
730 writel_relaxed(~(gpio->context.int_en[bank_num]), in zynq_gpio_restore_context()
731 gpio->base_addr + in zynq_gpio_restore_context()
733 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_restore_context()
740 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_suspend() local
741 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_suspend()
745 return -EINVAL; in zynq_gpio_suspend()
749 disable_irq(gpio->irq); in zynq_gpio_suspend()
752 zynq_gpio_save_context(gpio); in zynq_gpio_suspend()
761 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_resume() local
762 struct irq_data *data = irq_get_irq_data(gpio->irq); in zynq_gpio_resume()
767 return -EINVAL; in zynq_gpio_resume()
771 enable_irq(gpio->irq); in zynq_gpio_resume()
775 zynq_gpio_restore_context(gpio); in zynq_gpio_resume()
784 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_runtime_suspend() local
786 clk_disable_unprepare(gpio->clk); in zynq_gpio_runtime_suspend()
793 struct zynq_gpio *gpio = dev_get_drvdata(dev); in zynq_gpio_runtime_resume() local
795 return clk_prepare_enable(gpio->clk); in zynq_gpio_runtime_resume()
802 ret = pm_runtime_get_sync(chip->parent); in zynq_gpio_request()
813 pm_runtime_put(chip->parent); in zynq_gpio_free()
882 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
883 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
884 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
885 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
891 * zynq_gpio_probe - Initialization method for a zynq_gpio device
894 * This function allocates memory resources for the gpio device and registers
895 * all the banks of the device. It will also set up interrupts for the gpio
904 struct zynq_gpio *gpio; in zynq_gpio_probe() local
909 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in zynq_gpio_probe()
910 if (!gpio) in zynq_gpio_probe()
911 return -ENOMEM; in zynq_gpio_probe()
913 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); in zynq_gpio_probe()
915 dev_err(&pdev->dev, "of_match_node() failed\n"); in zynq_gpio_probe()
916 return -EINVAL; in zynq_gpio_probe()
918 gpio->p_data = match->data; in zynq_gpio_probe()
919 platform_set_drvdata(pdev, gpio); in zynq_gpio_probe()
921 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); in zynq_gpio_probe()
922 if (IS_ERR(gpio->base_addr)) in zynq_gpio_probe()
923 return PTR_ERR(gpio->base_addr); in zynq_gpio_probe()
925 gpio->irq = platform_get_irq(pdev, 0); in zynq_gpio_probe()
926 if (gpio->irq < 0) in zynq_gpio_probe()
927 return gpio->irq; in zynq_gpio_probe()
929 /* configure the gpio chip */ in zynq_gpio_probe()
930 chip = &gpio->chip; in zynq_gpio_probe()
931 chip->label = gpio->p_data->label; in zynq_gpio_probe()
932 chip->owner = THIS_MODULE; in zynq_gpio_probe()
933 chip->parent = &pdev->dev; in zynq_gpio_probe()
934 chip->get = zynq_gpio_get_value; in zynq_gpio_probe()
935 chip->set = zynq_gpio_set_value; in zynq_gpio_probe()
936 chip->request = zynq_gpio_request; in zynq_gpio_probe()
937 chip->free = zynq_gpio_free; in zynq_gpio_probe()
938 chip->direction_input = zynq_gpio_dir_in; in zynq_gpio_probe()
939 chip->direction_output = zynq_gpio_dir_out; in zynq_gpio_probe()
940 chip->get_direction = zynq_gpio_get_direction; in zynq_gpio_probe()
941 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); in zynq_gpio_probe()
942 chip->ngpio = gpio->p_data->ngpio; in zynq_gpio_probe()
944 /* Retrieve GPIO clock */ in zynq_gpio_probe()
945 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in zynq_gpio_probe()
946 if (IS_ERR(gpio->clk)) in zynq_gpio_probe()
947 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n"); in zynq_gpio_probe()
949 spin_lock_init(&gpio->dirlock); in zynq_gpio_probe()
951 pm_runtime_set_active(&pdev->dev); in zynq_gpio_probe()
952 pm_runtime_enable(&pdev->dev); in zynq_gpio_probe()
953 ret = pm_runtime_resume_and_get(&pdev->dev); in zynq_gpio_probe()
958 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { in zynq_gpio_probe()
959 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + in zynq_gpio_probe()
961 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) in zynq_gpio_probe()
965 /* Set up the GPIO irqchip */ in zynq_gpio_probe()
966 girq = &chip->irq; in zynq_gpio_probe()
968 girq->parent_handler = zynq_gpio_irqhandler; in zynq_gpio_probe()
969 girq->num_parents = 1; in zynq_gpio_probe()
970 girq->parents = devm_kcalloc(&pdev->dev, 1, in zynq_gpio_probe()
971 sizeof(*girq->parents), in zynq_gpio_probe()
973 if (!girq->parents) { in zynq_gpio_probe()
974 ret = -ENOMEM; in zynq_gpio_probe()
977 girq->parents[0] = gpio->irq; in zynq_gpio_probe()
978 girq->default_type = IRQ_TYPE_NONE; in zynq_gpio_probe()
979 girq->handler = handle_level_irq; in zynq_gpio_probe()
981 /* report a bug if gpio chip registration fails */ in zynq_gpio_probe()
982 ret = gpiochip_add_data(chip, gpio); in zynq_gpio_probe()
984 dev_err(&pdev->dev, "Failed to add gpio chip\n"); in zynq_gpio_probe()
988 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY); in zynq_gpio_probe()
989 device_init_wakeup(&pdev->dev, 1); in zynq_gpio_probe()
990 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
995 pm_runtime_put(&pdev->dev); in zynq_gpio_probe()
997 pm_runtime_disable(&pdev->dev); in zynq_gpio_probe()
1003 * zynq_gpio_remove - Driver removal function
1010 struct zynq_gpio *gpio = platform_get_drvdata(pdev); in zynq_gpio_remove() local
1013 ret = pm_runtime_get_sync(&pdev->dev); in zynq_gpio_remove()
1015 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n"); in zynq_gpio_remove()
1016 device_init_wakeup(&pdev->dev, 0); in zynq_gpio_remove()
1017 gpiochip_remove(&gpio->chip); in zynq_gpio_remove()
1018 device_set_wakeup_capable(&pdev->dev, 0); in zynq_gpio_remove()
1019 pm_runtime_disable(&pdev->dev); in zynq_gpio_remove()
1035 MODULE_DESCRIPTION("Zynq GPIO driver");