Lines Matching +full:tri +full:- +full:default +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
45 * struct xgpio_instance - Stores information about GPIO device
78 return bitmap_bitremap(bit, chip->hw_map, chip->sw_map, 64); in xgpio_from_bit()
83 return bitmap_bitremap(gpio, chip->sw_map, chip->hw_map, 64); in xgpio_to_bit()
110 default: in xgpio_regoffset()
111 return -EINVAL; in xgpio_regoffset()
117 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_read_ch()
124 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); in xgpio_write_ch()
131 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); in xgpio_read_ch_all()
139 int bit, lastbit = xgpio_to_bit(chip, chip->gc.ngpio - 1); in xgpio_write_ch_all()
146 * xgpio_get - Read the specified signal of the GPIO device.
168 * xgpio_set - Write the specified signal of the GPIO device.
182 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_set()
185 __assign_bit(bit, chip->state, val); in xgpio_set()
187 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); in xgpio_set()
189 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_set()
193 * xgpio_set_multiple - Write the specified signals of the GPIO device.
210 bitmap_remap(hw_mask, mask, chip->sw_map, chip->hw_map, 64); in xgpio_set_multiple()
211 bitmap_remap(hw_bits, bits, chip->sw_map, chip->hw_map, 64); in xgpio_set_multiple()
213 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_set_multiple()
215 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); in xgpio_set_multiple()
219 bitmap_copy(chip->state, state, 64); in xgpio_set_multiple()
221 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_set_multiple()
225 * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
230 * 0 - if direction of GPIO signals is set as input
239 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_dir_in()
242 __set_bit(bit, chip->dir); in xgpio_dir_in()
243 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); in xgpio_dir_in()
245 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_dir_in()
251 * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
268 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_dir_out()
271 __assign_bit(bit, chip->state, val); in xgpio_dir_out()
272 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); in xgpio_dir_out()
275 __clear_bit(bit, chip->dir); in xgpio_dir_out()
276 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); in xgpio_dir_out()
278 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_dir_out()
284 * xgpio_save_regs - Set initial values of GPIO pins
289 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); in xgpio_save_regs()
290 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); in xgpio_save_regs()
297 ret = pm_runtime_get_sync(chip->parent); in xgpio_request()
307 pm_runtime_put(chip->parent); in xgpio_free()
313 struct irq_data *data = irq_get_irq_data(gpio->irq); in xgpio_suspend()
327 * xgpio_remove - Remove method for the GPIO device.
336 pm_runtime_get_sync(&pdev->dev); in xgpio_remove()
337 pm_runtime_put_noidle(&pdev->dev); in xgpio_remove()
338 pm_runtime_disable(&pdev->dev); in xgpio_remove()
342 * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
354 struct irq_data *data = irq_get_irq_data(gpio->irq); in xgpio_resume()
371 clk_disable(gpio->clk); in xgpio_runtime_suspend()
380 return clk_enable(gpio->clk); in xgpio_runtime_resume()
390 * xgpio_irq_mask - Write the specified signal of the GPIO device.
401 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_irq_mask()
403 __clear_bit(bit, chip->enable); in xgpio_irq_mask()
405 if (xgpio_get_value32(chip->enable, bit) == 0) { in xgpio_irq_mask()
407 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); in xgpio_irq_mask()
409 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); in xgpio_irq_mask()
411 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_irq_mask()
413 gpiochip_disable_irq(&chip->gc, irq_offset); in xgpio_irq_mask()
417 * xgpio_irq_unmask - Write the specified signal of the GPIO device.
426 u32 old_enable = xgpio_get_value32(chip->enable, bit); in xgpio_irq_unmask()
429 gpiochip_enable_irq(&chip->gc, irq_offset); in xgpio_irq_unmask()
431 spin_lock_irqsave(&chip->gpio_lock, flags); in xgpio_irq_unmask()
433 __set_bit(bit, chip->enable); in xgpio_irq_unmask()
436 /* Clear any existing per-channel interrupts */ in xgpio_irq_unmask()
437 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); in xgpio_irq_unmask()
439 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); in xgpio_irq_unmask()
442 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); in xgpio_irq_unmask()
445 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); in xgpio_irq_unmask()
447 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); in xgpio_irq_unmask()
450 spin_unlock_irqrestore(&chip->gpio_lock, flags); in xgpio_irq_unmask()
454 * xgpio_set_irq_type - Write the specified signal of the GPIO device.
459 * 0 if interrupt type is supported otherwise -EINVAL
475 __set_bit(bit, chip->rising_edge); in xgpio_set_irq_type()
476 __set_bit(bit, chip->falling_edge); in xgpio_set_irq_type()
479 __set_bit(bit, chip->rising_edge); in xgpio_set_irq_type()
480 __clear_bit(bit, chip->falling_edge); in xgpio_set_irq_type()
483 __clear_bit(bit, chip->rising_edge); in xgpio_set_irq_type()
484 __set_bit(bit, chip->falling_edge); in xgpio_set_irq_type()
486 default: in xgpio_set_irq_type()
487 return -EINVAL; in xgpio_set_irq_type()
495 * xgpio_irqhandler - Gpio interrupt service routine
501 struct gpio_chip *gc = &chip->gc; in xgpio_irqhandler()
510 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); in xgpio_irqhandler()
511 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); in xgpio_irqhandler()
515 spin_lock(&chip->gpio_lock); in xgpio_irqhandler()
519 bitmap_complement(rising, chip->last_irq_read, 64); in xgpio_irqhandler()
521 bitmap_and(rising, rising, chip->enable, 64); in xgpio_irqhandler()
522 bitmap_and(rising, rising, chip->rising_edge, 64); in xgpio_irqhandler()
525 bitmap_and(falling, falling, chip->last_irq_read, 64); in xgpio_irqhandler()
526 bitmap_and(falling, falling, chip->enable, 64); in xgpio_irqhandler()
527 bitmap_and(falling, falling, chip->falling_edge, 64); in xgpio_irqhandler()
529 bitmap_copy(chip->last_irq_read, all, 64); in xgpio_irqhandler()
532 spin_unlock(&chip->gpio_lock); in xgpio_irqhandler()
534 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); in xgpio_irqhandler()
538 generic_handle_domain_irq(gc->irq.domain, irq_offset); in xgpio_irqhandler()
545 .name = "gpio-xilinx",
555 * xgpio_probe - Probe method for the GPIO device.
566 struct device_node *np = pdev->dev.of_node; in xgpio_probe()
568 u32 width[2]; in xgpio_probe()
569 u32 state[2]; in xgpio_probe()
570 u32 dir[2]; in xgpio_probe()
574 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); in xgpio_probe()
576 return -ENOMEM; in xgpio_probe()
580 /* First, check if the device is dual-channel */ in xgpio_probe()
581 of_property_read_u32(np, "xlnx,is-dual", &is_dual); in xgpio_probe()
588 /* Update GPIO state shadow register with default value */ in xgpio_probe()
589 of_property_read_u32(np, "xlnx,dout-default", &state[0]); in xgpio_probe()
590 of_property_read_u32(np, "xlnx,dout-default-2", &state[1]); in xgpio_probe()
592 bitmap_from_arr32(chip->state, state, 64); in xgpio_probe()
594 /* Update GPIO direction shadow register with default value */ in xgpio_probe()
595 of_property_read_u32(np, "xlnx,tri-default", &dir[0]); in xgpio_probe()
596 of_property_read_u32(np, "xlnx,tri-default-2", &dir[1]); in xgpio_probe()
598 bitmap_from_arr32(chip->dir, dir, 64); in xgpio_probe()
602 * and assume default width of 32 in xgpio_probe()
604 if (of_property_read_u32(np, "xlnx,gpio-width", &width[0])) in xgpio_probe()
608 return -EINVAL; in xgpio_probe()
610 if (is_dual && of_property_read_u32(np, "xlnx,gpio2-width", &width[1])) in xgpio_probe()
614 return -EINVAL; in xgpio_probe()
617 bitmap_set(chip->sw_map, 0, width[0] + width[1]); in xgpio_probe()
620 bitmap_set(chip->hw_map, 0, width[0]); in xgpio_probe()
621 bitmap_set(chip->hw_map, 32, width[1]); in xgpio_probe()
623 spin_lock_init(&chip->gpio_lock); in xgpio_probe()
625 chip->gc.base = -1; in xgpio_probe()
626 chip->gc.ngpio = bitmap_weight(chip->hw_map, 64); in xgpio_probe()
627 chip->gc.parent = &pdev->dev; in xgpio_probe()
628 chip->gc.direction_input = xgpio_dir_in; in xgpio_probe()
629 chip->gc.direction_output = xgpio_dir_out; in xgpio_probe()
630 chip->gc.get = xgpio_get; in xgpio_probe()
631 chip->gc.set = xgpio_set; in xgpio_probe()
632 chip->gc.request = xgpio_request; in xgpio_probe()
633 chip->gc.free = xgpio_free; in xgpio_probe()
634 chip->gc.set_multiple = xgpio_set_multiple; in xgpio_probe()
636 chip->gc.label = dev_name(&pdev->dev); in xgpio_probe()
638 chip->regs = devm_platform_ioremap_resource(pdev, 0); in xgpio_probe()
639 if (IS_ERR(chip->regs)) { in xgpio_probe()
640 dev_err(&pdev->dev, "failed to ioremap memory resource\n"); in xgpio_probe()
641 return PTR_ERR(chip->regs); in xgpio_probe()
644 chip->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in xgpio_probe()
645 if (IS_ERR(chip->clk)) in xgpio_probe()
646 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); in xgpio_probe()
648 pm_runtime_get_noresume(&pdev->dev); in xgpio_probe()
649 pm_runtime_set_active(&pdev->dev); in xgpio_probe()
650 pm_runtime_enable(&pdev->dev); in xgpio_probe()
654 chip->irq = platform_get_irq_optional(pdev, 0); in xgpio_probe()
655 if (chip->irq <= 0) in xgpio_probe()
658 /* Disable per-channel interrupts */ in xgpio_probe()
659 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); in xgpio_probe()
660 /* Clear any existing per-channel interrupts */ in xgpio_probe()
661 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); in xgpio_probe()
662 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); in xgpio_probe()
664 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); in xgpio_probe()
666 girq = &chip->gc.irq; in xgpio_probe()
668 girq->parent_handler = xgpio_irqhandler; in xgpio_probe()
669 girq->num_parents = 1; in xgpio_probe()
670 girq->parents = devm_kcalloc(&pdev->dev, 1, in xgpio_probe()
671 sizeof(*girq->parents), in xgpio_probe()
673 if (!girq->parents) { in xgpio_probe()
674 status = -ENOMEM; in xgpio_probe()
677 girq->parents[0] = chip->irq; in xgpio_probe()
678 girq->default_type = IRQ_TYPE_NONE; in xgpio_probe()
679 girq->handler = handle_bad_irq; in xgpio_probe()
682 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); in xgpio_probe()
684 dev_err(&pdev->dev, "failed to add GPIO chip\n"); in xgpio_probe()
688 pm_runtime_put(&pdev->dev); in xgpio_probe()
692 pm_runtime_disable(&pdev->dev); in xgpio_probe()
693 pm_runtime_put_noidle(&pdev->dev); in xgpio_probe()
698 { .compatible = "xlnx,xps-gpio-1.00.a", },
708 .name = "gpio-xilinx",