Lines Matching full:chip
46 * @gc: GPIO chip
74 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch)
86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
96 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
102 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
104 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);
108 xgpio_read_ch(chip, reg, bit, a);
111 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a)
113 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);
117 xgpio_write_ch(chip, reg, bit, a);
133 struct xgpio_instance *chip = gpiochip_get_data(gc);
134 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
137 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);
154 struct xgpio_instance *chip = gpiochip_get_data(gc);
155 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
157 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
160 __assign_bit(bit, chip->state, val);
162 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
164 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
185 struct xgpio_instance *chip = gpiochip_get_data(gc);
187 bitmap_scatter(hw_mask, mask, chip->map, 64);
188 bitmap_scatter(hw_bits, bits, chip->map, 64);
190 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
192 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);
194 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);
196 bitmap_copy(chip->state, state, 64);
198 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
215 struct xgpio_instance *chip = gpiochip_get_data(gc);
216 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
218 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
221 __set_bit(bit, chip->dir);
222 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
224 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
238 * If all GPIO signals of GPIO chip is configured as input then it returns
244 struct xgpio_instance *chip = gpiochip_get_data(gc);
245 unsigned long bit = find_nth_bit(chip->map, 64, gpio);
247 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
250 __assign_bit(bit, chip->state, val);
251 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);
254 __clear_bit(bit, chip->dir);
255 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);
257 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
264 * @chip: Pointer to GPIO instance
266 static void xgpio_save_regs(struct xgpio_instance *chip)
268 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);
269 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);
272 static int xgpio_request(struct gpio_chip *chip, unsigned int offset)
276 ret = pm_runtime_get_sync(chip->parent);
284 static void xgpio_free(struct gpio_chip *chip, unsigned int offset)
286 pm_runtime_put(chip->parent);
322 * @irq_data: per IRQ and chip data passed down to chip functions
369 * @irq_data: per IRQ and chip data passed down to chip functions
374 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
376 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;
379 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
381 __clear_bit(bit, chip->enable);
383 enable = bitmap_read(chip->enable, round_down(bit, 32), 32);
386 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
388 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);
390 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
392 gpiochip_disable_irq(&chip->gc, irq_offset);
397 * @irq_data: per IRQ and chip data passed down to chip functions
402 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
404 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;
407 gpiochip_enable_irq(&chip->gc, irq_offset);
409 raw_spin_lock_irqsave(&chip->gpio_lock, flags);
411 enable = bitmap_read(chip->enable, round_down(bit, 32), 32);
414 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
416 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);
419 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);
422 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);
424 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);
427 __set_bit(bit, chip->enable);
429 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
434 * @irq_data: Per IRQ and chip data passed down to chip functions
442 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data);
444 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset);
454 __set_bit(bit, chip->rising_edge);
455 __set_bit(bit, chip->falling_edge);
458 __set_bit(bit, chip->rising_edge);
459 __clear_bit(bit, chip->falling_edge);
462 __clear_bit(bit, chip->rising_edge);
463 __set_bit(bit, chip->falling_edge);
479 struct xgpio_instance *chip = irq_desc_get_handler_data(desc);
480 struct gpio_chip *gc = &chip->gc;
489 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
490 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);
494 raw_spin_lock(&chip->gpio_lock);
496 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw);
498 bitmap_complement(rising, chip->last_irq_read, 64);
500 bitmap_and(rising, rising, chip->enable, 64);
501 bitmap_and(rising, rising, chip->rising_edge, 64);
504 bitmap_and(falling, falling, chip->last_irq_read, 64);
505 bitmap_and(falling, falling, chip->enable, 64);
506 bitmap_and(falling, falling, chip->falling_edge, 64);
508 bitmap_copy(chip->last_irq_read, hw, 64);
511 raw_spin_unlock(&chip->gpio_lock);
515 bitmap_gather(sw, hw, chip->map, 64);
543 struct xgpio_instance *chip;
552 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
553 if (!chip)
556 platform_set_drvdata(pdev, chip);
570 bitmap_from_arr32(chip->state, state, 64);
576 bitmap_from_arr32(chip->dir, dir, 64);
595 bitmap_set(chip->map, 0, width[0]);
596 bitmap_set(chip->map, 32, width[1]);
598 raw_spin_lock_init(&chip->gpio_lock);
600 chip->gc.base = -1;
601 chip->gc.ngpio = bitmap_weight(chip->map, 64);
602 chip->gc.parent = dev;
603 chip->gc.direction_input = xgpio_dir_in;
604 chip->gc.direction_output = xgpio_dir_out;
605 chip->gc.get = xgpio_get;
606 chip->gc.set = xgpio_set;
607 chip->gc.request = xgpio_request;
608 chip->gc.free = xgpio_free;
609 chip->gc.set_multiple = xgpio_set_multiple;
611 chip->gc.label = dev_name(dev);
613 chip->regs = devm_platform_ioremap_resource(pdev, 0);
614 if (IS_ERR(chip->regs)) {
616 return PTR_ERR(chip->regs);
619 chip->clk = devm_clk_get_optional_enabled(dev, NULL);
620 if (IS_ERR(chip->clk))
621 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n");
627 xgpio_save_regs(chip);
629 chip->irq = platform_get_irq_optional(pdev, 0);
630 if (chip->irq <= 0)
634 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);
636 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);
637 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);
639 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);
641 girq = &chip->gc.irq;
651 girq->parents[0] = chip->irq;
656 status = devm_gpiochip_add_data(dev, &chip->gc, chip);
658 dev_err(dev, "failed to add GPIO chip\n");