1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2008 - 2013 Xilinx, Inc.
45  * struct xgpio_instance - Stores information about GPIO device
49  * @state: GPIO write state shadow register
50  * @last_irq_read: GPIO read state register from last interrupt
63 	DECLARE_BITMAP(state, 64);
82 		return -EINVAL;  in xgpio_regoffset()
88 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_read_ch()
96 	void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);  in xgpio_write_ch()
104 	unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);  in xgpio_read_ch_all()
113 	unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1);  in xgpio_write_ch_all()
121  * xgpio_get - Read the specified signal of the GPIO device.
134 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_get()
135 	DECLARE_BITMAP(state, 64);  in xgpio_get()
137 	xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state);  in xgpio_get()
139 	return test_bit(bit, state);  in xgpio_get()
143  * xgpio_set - Write the specified signal of the GPIO device.
155 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_set()
157 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set()
160 	__assign_bit(bit, chip->state, val);  in xgpio_set()
162 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_set()
164 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set()
170  * xgpio_set_multiple - Write the specified signals of the GPIO device.
183 	DECLARE_BITMAP(state, 64);  in xgpio_set_multiple()
187 	bitmap_scatter(hw_mask, mask, chip->map, 64);  in xgpio_set_multiple()
188 	bitmap_scatter(hw_bits, bits, chip->map, 64);  in xgpio_set_multiple()
190 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_set_multiple()
192 	bitmap_replace(state, chip->state, hw_bits, hw_mask, 64);  in xgpio_set_multiple()
194 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state);  in xgpio_set_multiple()
196 	bitmap_copy(chip->state, state, 64);  in xgpio_set_multiple()
198 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_set_multiple()
204  * xgpio_dir_in - Set the direction of the specified GPIO signal as input.
209  * 0 - if direction of GPIO signals is set as input
216 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_dir_in()
218 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_in()
221 	__set_bit(bit, chip->dir);  in xgpio_dir_in()
222 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_in()
224 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_in()
230  * xgpio_dir_out - Set the direction of the specified GPIO signal as output.
245 	unsigned long bit = find_nth_bit(chip->map, 64, gpio);  in xgpio_dir_out()
247 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_dir_out()
249 	/* Write state of GPIO signal */  in xgpio_dir_out()
250 	__assign_bit(bit, chip->state, val);  in xgpio_dir_out()
251 	xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state);  in xgpio_dir_out()
254 	__clear_bit(bit, chip->dir);  in xgpio_dir_out()
255 	xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir);  in xgpio_dir_out()
257 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_dir_out()
263  * xgpio_save_regs - Set initial values of GPIO pins
268 	xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state);  in xgpio_save_regs()
269 	xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir);  in xgpio_save_regs()
276 	ret = pm_runtime_get_sync(chip->parent);  in xgpio_request()
286 	pm_runtime_put(chip->parent);  in xgpio_free()
292 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_suspend()
306  * xgpio_remove - Remove method for the GPIO device.
315 	pm_runtime_get_sync(&pdev->dev);  in xgpio_remove()
316 	pm_runtime_put_noidle(&pdev->dev);  in xgpio_remove()
317 	pm_runtime_disable(&pdev->dev);  in xgpio_remove()
321  * xgpio_irq_ack - Acknowledge a child GPIO interrupt.
333 	struct irq_data *data = irq_get_irq_data(gpio->irq);  in xgpio_resume()
350 	clk_disable(gpio->clk);  in xgpio_runtime_suspend()
359 	return clk_enable(gpio->clk);  in xgpio_runtime_resume()
369  * xgpio_irq_mask - Write the specified signal of the GPIO device.
377 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;  in xgpio_irq_mask()
380 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_mask()
382 	__clear_bit(bit, chip->enable);  in xgpio_irq_mask()
384 	enable = bitmap_read(chip->enable, round_down(bit, 32), 32);  in xgpio_irq_mask()
387 		temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_mask()
389 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp);  in xgpio_irq_mask()
391 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_mask()
393 	gpiochip_disable_irq(&chip->gc, irq_offset);  in xgpio_irq_mask()
397  * xgpio_irq_unmask - Write the specified signal of the GPIO device.
405 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable;  in xgpio_irq_unmask()
408 	gpiochip_enable_irq(&chip->gc, irq_offset);  in xgpio_irq_unmask()
410 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
412 	enable = bitmap_read(chip->enable, round_down(bit, 32), 32);  in xgpio_irq_unmask()
414 		/* Clear any existing per-channel interrupts */  in xgpio_irq_unmask()
415 		val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irq_unmask()
417 		xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val);  in xgpio_irq_unmask()
420 		xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read);  in xgpio_irq_unmask()
423 		val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET);  in xgpio_irq_unmask()
425 		xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val);  in xgpio_irq_unmask()
428 	__set_bit(bit, chip->enable);  in xgpio_irq_unmask()
430 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);  in xgpio_irq_unmask()
434  * xgpio_set_irq_type - Write the specified signal of the GPIO device.
439  * 0 if interrupt type is supported otherwise -EINVAL
445 	unsigned long bit = find_nth_bit(chip->map, 64, irq_offset);  in xgpio_set_irq_type()
449 	 * indication for any state change in a given GPIO channel (bank).  in xgpio_set_irq_type()
455 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
456 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
459 		__set_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
460 		__clear_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
463 		__clear_bit(bit, chip->rising_edge);  in xgpio_set_irq_type()
464 		__set_bit(bit, chip->falling_edge);  in xgpio_set_irq_type()
467 		return -EINVAL;  in xgpio_set_irq_type()
475  * xgpio_irqhandler - Gpio interrupt service routine
481 	struct gpio_chip *gc = &chip->gc;  in xgpio_irqhandler()
490 	status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_irqhandler()
491 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status);  in xgpio_irqhandler()
495 	raw_spin_lock(&chip->gpio_lock);  in xgpio_irqhandler()
499 	bitmap_complement(rising, chip->last_irq_read, 64);  in xgpio_irqhandler()
501 	bitmap_and(rising, rising, chip->enable, 64);  in xgpio_irqhandler()
502 	bitmap_and(rising, rising, chip->rising_edge, 64);  in xgpio_irqhandler()
505 	bitmap_and(falling, falling, chip->last_irq_read, 64);  in xgpio_irqhandler()
506 	bitmap_and(falling, falling, chip->enable, 64);  in xgpio_irqhandler()
507 	bitmap_and(falling, falling, chip->falling_edge, 64);  in xgpio_irqhandler()
509 	bitmap_copy(chip->last_irq_read, hw, 64);  in xgpio_irqhandler()
512 	raw_spin_unlock(&chip->gpio_lock);  in xgpio_irqhandler()
514 	dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling);  in xgpio_irqhandler()
516 	bitmap_gather(sw, hw, chip->map, 64);  in xgpio_irqhandler()
518 		generic_handle_domain_irq(gc->irq.domain, irq_offset);  in xgpio_irqhandler()
524 	.name = "gpio-xilinx",
534  * xgpio_probe - Probe method for the GPIO device.
543 	struct device *dev = &pdev->dev;  in xgpio_probe()
548 	u32 state[2];  in xgpio_probe()  local
555 		return -ENOMEM;  in xgpio_probe()
559 	/* First, check if the device is dual-channel */  in xgpio_probe()
560 	device_property_read_u32(dev, "xlnx,is-dual", &is_dual);  in xgpio_probe()
564 	memset32(state, 0, ARRAY_SIZE(state));  in xgpio_probe()
567 	/* Update GPIO state shadow register with default value */  in xgpio_probe()
568 	device_property_read_u32(dev, "xlnx,dout-default", &state[0]);  in xgpio_probe()
569 	device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]);  in xgpio_probe()
571 	bitmap_from_arr32(chip->state, state, 64);  in xgpio_probe()
574 	device_property_read_u32(dev, "xlnx,tri-default", &dir[0]);  in xgpio_probe()
575 	device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]);  in xgpio_probe()
577 	bitmap_from_arr32(chip->dir, dir, 64);  in xgpio_probe()
583 	if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0]))  in xgpio_probe()
587 		return -EINVAL;  in xgpio_probe()
589 	if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1]))  in xgpio_probe()
593 		return -EINVAL;  in xgpio_probe()
596 	bitmap_set(chip->map,  0, width[0]);  in xgpio_probe()
597 	bitmap_set(chip->map, 32, width[1]);  in xgpio_probe()
599 	raw_spin_lock_init(&chip->gpio_lock);  in xgpio_probe()
601 	chip->gc.base = -1;  in xgpio_probe()
602 	chip->gc.ngpio = bitmap_weight(chip->map, 64);  in xgpio_probe()
603 	chip->gc.parent = dev;  in xgpio_probe()
604 	chip->gc.direction_input = xgpio_dir_in;  in xgpio_probe()
605 	chip->gc.direction_output = xgpio_dir_out;  in xgpio_probe()
606 	chip->gc.get = xgpio_get;  in xgpio_probe()
607 	chip->gc.set = xgpio_set;  in xgpio_probe()
608 	chip->gc.request = xgpio_request;  in xgpio_probe()
609 	chip->gc.free = xgpio_free;  in xgpio_probe()
610 	chip->gc.set_multiple = xgpio_set_multiple;  in xgpio_probe()
612 	chip->gc.label = dev_name(dev);  in xgpio_probe()
614 	chip->regs = devm_platform_ioremap_resource(pdev, 0);  in xgpio_probe()
615 	if (IS_ERR(chip->regs)) {  in xgpio_probe()
617 		return PTR_ERR(chip->regs);  in xgpio_probe()
620 	chip->clk = devm_clk_get_optional_enabled(dev, NULL);  in xgpio_probe()
621 	if (IS_ERR(chip->clk))  in xgpio_probe()
622 		return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n");  in xgpio_probe()
630 	chip->irq = platform_get_irq_optional(pdev, 0);  in xgpio_probe()
631 	if (chip->irq <= 0)  in xgpio_probe()
634 	/* Disable per-channel interrupts */  in xgpio_probe()
635 	xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0);  in xgpio_probe()
636 	/* Clear any existing per-channel interrupts */  in xgpio_probe()
637 	temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET);  in xgpio_probe()
638 	xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp);  in xgpio_probe()
640 	xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE);  in xgpio_probe()
642 	girq = &chip->gc.irq;  in xgpio_probe()
644 	girq->parent_handler = xgpio_irqhandler;  in xgpio_probe()
645 	girq->num_parents = 1;  in xgpio_probe()
646 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),  in xgpio_probe()
648 	if (!girq->parents) {  in xgpio_probe()
649 		status = -ENOMEM;  in xgpio_probe()
652 	girq->parents[0] = chip->irq;  in xgpio_probe()
653 	girq->default_type = IRQ_TYPE_NONE;  in xgpio_probe()
654 	girq->handler = handle_bad_irq;  in xgpio_probe()
657 	status = devm_gpiochip_add_data(dev, &chip->gc, chip);  in xgpio_probe()
673 	{ .compatible = "xlnx,xps-gpio-1.00.a", },
683 			.name = "gpio-xilinx",