1 // SPDX-License-Identifier: GPL-2.0
35  * Document Number: 328195-001
55 	if (gpio >= sch->resume_base) {  in sch_gpio_offset()
56 		gpio -= sch->resume_base;  in sch_gpio_offset()
65 	if (gpio >= sch->resume_base)  in sch_gpio_bit()
66 		gpio -= sch->resume_base;  in sch_gpio_bit()
78 	reg_val = !!(ioread8(sch->regs + offset) & BIT(bit));  in sch_gpio_reg_get()
92 	reg_val = ioread8(sch->regs + offset);  in sch_gpio_reg_set()
99 	iowrite8(reg_val, sch->regs + offset);  in sch_gpio_reg_set()
107 	spin_lock_irqsave(&sch->lock, flags);  in sch_gpio_direction_in()
109 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_gpio_direction_in()
125 	spin_lock_irqsave(&sch->lock, flags);  in sch_gpio_set()
127 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_gpio_set()
136 	spin_lock_irqsave(&sch->lock, flags);  in sch_gpio_direction_out()
138 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_gpio_direction_out()
143 	 * Actually the level register is read-only when configured as input.  in sch_gpio_direction_out()
147 	 * and an external pull-up is connected.  in sch_gpio_direction_out()
179 	int rising, falling;  in sch_irq_type()  local
184 		falling = 0;  in sch_irq_type()
188 		falling = 1;  in sch_irq_type()
192 		falling = 1;  in sch_irq_type()
195 		return -EINVAL;  in sch_irq_type()
198 	spin_lock_irqsave(&sch->lock, flags);  in sch_irq_type()
201 	sch_gpio_reg_set(sch, gpio_num, GTNE, falling);  in sch_irq_type()
205 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_irq_type()
217 	spin_lock_irqsave(&sch->lock, flags);  in sch_irq_ack()
219 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_irq_ack()
227 	spin_lock_irqsave(&sch->lock, flags);  in sch_irq_mask_unmask()
229 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_irq_mask_unmask()
263 	struct gpio_chip *gc = &sch->chip;  in sch_gpio_gpe_handler()
270 	spin_lock_irqsave(&sch->lock, flags);  in sch_gpio_gpe_handler()
272 	core_status = ioread32(sch->regs + CORE_BANK_OFFSET + GTS);  in sch_gpio_gpe_handler()
273 	resume_status = ioread32(sch->regs + RESUME_BANK_OFFSET + GTS);  in sch_gpio_gpe_handler()
275 	spin_unlock_irqrestore(&sch->lock, flags);  in sch_gpio_gpe_handler()
277 	pending = (resume_status << sch->resume_base) | core_status;  in sch_gpio_gpe_handler()
278 	for_each_set_bit(offset, &pending, sch->chip.ngpio)  in sch_gpio_gpe_handler()
279 		generic_handle_domain_irq(gc->irq.domain, offset);  in sch_gpio_gpe_handler()
294 	acpi_disable_gpe(NULL, sch->gpe);  in sch_gpio_remove_gpe_handler()
295 	acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);  in sch_gpio_remove_gpe_handler()
300 	struct device *dev = sch->chip.parent;  in sch_gpio_install_gpe_handler()
303 	status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,  in sch_gpio_install_gpe_handler()
304 					  sch->gpe_handler, sch);  in sch_gpio_install_gpe_handler()
307 			sch->gpe, acpi_format_exception(status));  in sch_gpio_install_gpe_handler()
308 		return -ENODEV;  in sch_gpio_install_gpe_handler()
311 	status = acpi_enable_gpe(NULL, sch->gpe);  in sch_gpio_install_gpe_handler()
314 			sch->gpe, acpi_format_exception(status));  in sch_gpio_install_gpe_handler()
315 		acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);  in sch_gpio_install_gpe_handler()
316 		return -ENODEV;  in sch_gpio_install_gpe_handler()
324 	struct device *dev = &pdev->dev;  in sch_gpio_probe()
333 		return -ENOMEM;  in sch_gpio_probe()
337 		return -EBUSY;  in sch_gpio_probe()
339 	regs = devm_ioport_map(dev, res->start, resource_size(res));  in sch_gpio_probe()
341 		return -EBUSY;  in sch_gpio_probe()
343 	sch->regs = regs;  in sch_gpio_probe()
345 	spin_lock_init(&sch->lock);  in sch_gpio_probe()
346 	sch->chip = sch_gpio_chip;  in sch_gpio_probe()
347 	sch->chip.label = dev_name(dev);  in sch_gpio_probe()
348 	sch->chip.parent = dev;  in sch_gpio_probe()
350 	switch (pdev->id) {  in sch_gpio_probe()
352 		sch->resume_base = 10;  in sch_gpio_probe()
353 		sch->chip.ngpio = 14;  in sch_gpio_probe()
370 		sch->resume_base = 5;  in sch_gpio_probe()
371 		sch->chip.ngpio = 14;  in sch_gpio_probe()
375 		sch->resume_base = 21;  in sch_gpio_probe()
376 		sch->chip.ngpio = 30;  in sch_gpio_probe()
380 		sch->resume_base = 2;  in sch_gpio_probe()
381 		sch->chip.ngpio = 8;  in sch_gpio_probe()
385 		return -ENODEV;  in sch_gpio_probe()
388 	girq = &sch->chip.irq;  in sch_gpio_probe()
390 	girq->num_parents = 0;  in sch_gpio_probe()
391 	girq->parents = NULL;  in sch_gpio_probe()
392 	girq->parent_handler = NULL;  in sch_gpio_probe()
393 	girq->default_type = IRQ_TYPE_NONE;  in sch_gpio_probe()
394 	girq->handler = handle_bad_irq;  in sch_gpio_probe()
397 	sch->gpe = GPE0E_GPIO;  in sch_gpio_probe()
398 	sch->gpe_handler = sch_gpio_gpe_handler;  in sch_gpio_probe()
404 	return devm_gpiochip_add_data(dev, &sch->chip, sch);  in sch_gpio_probe()