1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Realtek DHC gpio driver
10 #include <linux/gpio/driver.h>
30  * struct rtd_gpio_info - Specific GPIO register information
31  * @name: GPIO device name
32  * @gpio_base: GPIO base number
34  * @dir_offset: Offset for GPIO direction registers
35  * @dato_offset: Offset for GPIO data output registers
36  * @dati_offset: Offset for GPIO data input registers
37  * @ie_offset: Offset for GPIO interrupt enable registers
38  * @dp_offset: Offset for GPIO detection polarity registers
39  * @gpa_offset: Offset for GPIO assert interrupt status registers
40  * @gpda_offset: Offset for GPIO deassert interrupt status registers
41  * @deb_offset: Offset for GPIO debounce registers
42  * @deb_val: Register values representing the GPIO debounce time
75 	*reg_offset = info->deb_offset[offset / 8];  in rtd_gpio_get_deb_setval()
77 	return info->deb_val[deb_index];  in rtd_gpio_get_deb_setval()
83 	*reg_offset = info->deb_offset[0];  in rtd1295_misc_gpio_get_deb_setval()
85 	return info->deb_val[deb_index];  in rtd1295_misc_gpio_get_deb_setval()
91 	*reg_offset = info->deb_offset[0];  in rtd1295_iso_gpio_get_deb_setval()
93 	return info->deb_val[deb_index];  in rtd1295_iso_gpio_get_deb_setval()
180 	return data->info->dir_offset[offset / 32];  in rtd_gpio_dir_offset()
185 	return data->info->dato_offset[offset / 32];  in rtd_gpio_dato_offset()
190 	return data->info->dati_offset[offset / 32];  in rtd_gpio_dati_offset()
195 	return data->info->ie_offset[offset / 32];  in rtd_gpio_ie_offset()
200 	return data->info->dp_offset[offset / 32];  in rtd_gpio_dp_offset()
206 	/* Each GPIO assert interrupt status register contains 31 GPIOs. */  in rtd_gpio_gpa_offset()
207 	return data->info->gpa_offset[offset / 31];  in rtd_gpio_gpa_offset()
212 	/* Each GPIO deassert interrupt status register contains 31 GPIOs. */  in rtd_gpio_gpda_offset()
213 	return data->info->gpda_offset[offset / 31];  in rtd_gpio_gpda_offset()
247 		return -ENOTSUPP;  in rtd_gpio_set_debounce()
250 	deb_val = data->info->get_deb_setval(data->info, offset, deb_index, &reg_offset, &shift);  in rtd_gpio_set_debounce()
254 	guard(raw_spinlock_irqsave)(&data->lock);  in rtd_gpio_set_debounce()
255 	writel_relaxed(val, data->base + reg_offset);  in rtd_gpio_set_debounce()
274 		return -ENOTSUPP;  in rtd_gpio_set_config()
287 	guard(raw_spinlock_irqsave)(&data->lock);  in rtd_gpio_set()
289 	val = readl_relaxed(data->base + dato_reg_offset);  in rtd_gpio_set()
294 	writel_relaxed(val, data->base + dato_reg_offset);  in rtd_gpio_set()
306 	guard(raw_spinlock_irqsave)(&data->lock);  in rtd_gpio_get()
308 	val = readl_relaxed(data->base + dir_reg_offset);  in rtd_gpio_get()
310 	val = readl_relaxed(data->base + dat_reg_offset);  in rtd_gpio_get()
322 	val = readl_relaxed(data->base + reg_offset);  in rtd_gpio_get_direction()
338 	guard(raw_spinlock_irqsave)(&data->lock);  in rtd_gpio_set_direction()
340 	val = readl_relaxed(data->base + reg_offset);  in rtd_gpio_set_direction()
345 	writel_relaxed(val, data->base + reg_offset);  in rtd_gpio_set_direction()
369 	enable = readl_relaxed(data->base + ie_reg_offset);  in rtd_gpio_check_ie()
376 	int (*get_reg_offset)(struct rtd_gpio *gpio, unsigned int offset);  in rtd_gpio_irq_handle()
378 	struct irq_domain *domain = data->gpio_chip.irq.domain;  in rtd_gpio_irq_handle()
385 	if (irq == data->irqs[0])  in rtd_gpio_irq_handle()
387 	else if (irq == data->irqs[1])  in rtd_gpio_irq_handle()
392 	/* Each GPIO interrupt status register contains 31 GPIOs. */  in rtd_gpio_irq_handle()
393 	for (i = 0; i < data->info->num_gpios; i += 31) {  in rtd_gpio_irq_handle()
401 		status = readl_relaxed(data->irq_base + reg_offset);  in rtd_gpio_irq_handle()
403 		writel_relaxed(status, data->irq_base + reg_offset);  in rtd_gpio_irq_handle()
406 			hwirq = i + j - 1;  in rtd_gpio_irq_handle()
411 				if ((irq == data->irqs[1]) && (irq_type != IRQ_TYPE_EDGE_BOTH))  in rtd_gpio_irq_handle()
442 	guard(raw_spinlock_irqsave)(&data->lock);  in rtd_gpio_enable_irq()
444 	writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset);  in rtd_gpio_enable_irq()
445 	writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset);  in rtd_gpio_enable_irq()
447 	val = readl_relaxed(data->base + ie_reg_offset);  in rtd_gpio_enable_irq()
449 	writel_relaxed(val, data->base + ie_reg_offset);  in rtd_gpio_enable_irq()
463 	scoped_guard(raw_spinlock_irqsave, &data->lock) {  in rtd_gpio_disable_irq()
464 		val = readl_relaxed(data->base + ie_reg_offset);  in rtd_gpio_disable_irq()
466 		writel_relaxed(val, data->base + ie_reg_offset);  in rtd_gpio_disable_irq()
498 		return -EINVAL;  in rtd_gpio_irq_set_type()
501 	scoped_guard(raw_spinlock_irqsave, &data->lock) {  in rtd_gpio_irq_set_type()
502 		val = readl_relaxed(data->base + dp_reg_offset);  in rtd_gpio_irq_set_type()
507 		writel_relaxed(val, data->base + dp_reg_offset);  in rtd_gpio_irq_set_type()
516 	.name = "rtd-gpio",
525 	struct device *dev = &pdev->dev;  in rtd_gpio_probe()
532 		return -ENOMEM;  in rtd_gpio_probe()
537 	data->irqs[0] = ret;  in rtd_gpio_probe()
542 	data->irqs[1] = ret;  in rtd_gpio_probe()
544 	data->info = device_get_match_data(dev);  in rtd_gpio_probe()
545 	if (!data->info)  in rtd_gpio_probe()
546 		return -EINVAL;  in rtd_gpio_probe()
548 	raw_spin_lock_init(&data->lock);  in rtd_gpio_probe()
550 	data->base = devm_platform_ioremap_resource(pdev, 0);  in rtd_gpio_probe()
551 	if (IS_ERR(data->base))  in rtd_gpio_probe()
552 		return PTR_ERR(data->base);  in rtd_gpio_probe()
554 	data->irq_base = devm_platform_ioremap_resource(pdev, 1);  in rtd_gpio_probe()
555 	if (IS_ERR(data->irq_base))  in rtd_gpio_probe()
556 		return PTR_ERR(data->irq_base);  in rtd_gpio_probe()
558 	data->gpio_chip.label = dev_name(dev);  in rtd_gpio_probe()
559 	data->gpio_chip.base = -1;  in rtd_gpio_probe()
560 	data->gpio_chip.ngpio = data->info->num_gpios;  in rtd_gpio_probe()
561 	data->gpio_chip.request = gpiochip_generic_request;  in rtd_gpio_probe()
562 	data->gpio_chip.free = gpiochip_generic_free;  in rtd_gpio_probe()
563 	data->gpio_chip.get_direction = rtd_gpio_get_direction;  in rtd_gpio_probe()
564 	data->gpio_chip.direction_input = rtd_gpio_direction_input;  in rtd_gpio_probe()
565 	data->gpio_chip.direction_output = rtd_gpio_direction_output;  in rtd_gpio_probe()
566 	data->gpio_chip.set = rtd_gpio_set;  in rtd_gpio_probe()
567 	data->gpio_chip.get = rtd_gpio_get;  in rtd_gpio_probe()
568 	data->gpio_chip.set_config = rtd_gpio_set_config;  in rtd_gpio_probe()
569 	data->gpio_chip.parent = dev;  in rtd_gpio_probe()
571 	irq_chip = &data->gpio_chip.irq;  in rtd_gpio_probe()
572 	irq_chip->handler = handle_bad_irq;  in rtd_gpio_probe()
573 	irq_chip->default_type = IRQ_TYPE_NONE;  in rtd_gpio_probe()
574 	irq_chip->parent_handler = rtd_gpio_irq_handle;  in rtd_gpio_probe()
575 	irq_chip->parent_handler_data = data;  in rtd_gpio_probe()
576 	irq_chip->num_parents = 2;  in rtd_gpio_probe()
577 	irq_chip->parents = data->irqs;  in rtd_gpio_probe()
581 	return devm_gpiochip_add_data(dev, &data->gpio_chip, data);  in rtd_gpio_probe()
585 	{ .compatible = "realtek,rtd1295-misc-gpio", .data = &rtd1295_misc_gpio_info },
586 	{ .compatible = "realtek,rtd1295-iso-gpio", .data = &rtd1295_iso_gpio_info },
587 	{ .compatible = "realtek,rtd1395-iso-gpio", .data = &rtd1395_iso_gpio_info },
588 	{ .compatible = "realtek,rtd1619-iso-gpio", .data = &rtd1619_iso_gpio_info },
589 	{ .compatible = "realtek,rtd1319-iso-gpio", .data = &rtd_iso_gpio_info },
590 	{ .compatible = "realtek,rtd1619b-iso-gpio", .data = &rtd_iso_gpio_info },
591 	{ .compatible = "realtek,rtd1319d-iso-gpio", .data = &rtd_iso_gpio_info },
592 	{ .compatible = "realtek,rtd1315e-iso-gpio", .data = &rtd_iso_gpio_info },
599 		.name = "gpio-rtd",
606 MODULE_DESCRIPTION("Realtek DHC SoC gpio driver");