1 // SPDX-License-Identifier: GPL-2.0-only
29 /* Two bits per GPIO in IMR registers */
42  * realtek_gpio_ctrl - Realtek Otto GPIO driver data
49  * @bank_read: Read a bank setting as a single 32-bit value
50  * @bank_write: Write a bank setting as a single 32-bit value
53  * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54  * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55  * a value from (to) these registers. The IMR register consists of four 16-bit
56  * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
57  * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
82 	 * Allow disabling interrupts, for cases where the port order is
83 	 * unknown. This may result in a port mismatch between ISR and IMR.
89 	 * Port order is reversed, meaning DCBA register layout for 1-bit
90 	 * fields, and [BA, DC] for 2-bit fields.
94 	 * Interrupts can be enabled per cpu. This requires a secondary IO
95 	 * range, where the per-cpu enable masks are located.
108  * Normal port order register access
110  * Port information is stored with the first port at offset 0, followed by the
111  * second, etc. Most registers store one bit per GPIO and use a u8 value per
112  * port. The two interrupt mask registers store two bits per GPIO, so use u16
128 	unsigned int port = line / 8;  in realtek_gpio_line_imr_pos_swapped()  local
130 	return 2 * (8 * (port ^ 1) + port_pin);  in realtek_gpio_line_imr_pos_swapped()
134  * Reversed port order register access
136  * For registers with one bit per GPIO, all ports are stored as u8-s in one
138  * per GPIO, so use u16 values. The first register contains ports 1 and 0, the
158 	ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask);  in realtek_gpio_clear_isr()
163 	return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR);  in realtek_gpio_read_isr()
169 	void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR;  in realtek_gpio_update_line_imr()
170 	unsigned int line_shift = ctrl->line_imr_pos(line);  in realtek_gpio_update_line_imr()
172 	u32 irq_type = ctrl->intr_type[line];  in realtek_gpio_update_line_imr()
173 	u32 irq_mask = ctrl->intr_mask[line];  in realtek_gpio_update_line_imr()
197 	gpiochip_enable_irq(&ctrl->gc, line);  in realtek_gpio_irq_unmask()
199 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in realtek_gpio_irq_unmask()
200 	ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK;  in realtek_gpio_irq_unmask()
202 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in realtek_gpio_irq_unmask()
211 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in realtek_gpio_irq_mask()
212 	ctrl->intr_mask[line] = 0;  in realtek_gpio_irq_mask()
214 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in realtek_gpio_irq_mask()
216 	gpiochip_disable_irq(&ctrl->gc, line);  in realtek_gpio_irq_mask()
237 		return -EINVAL;  in realtek_gpio_irq_set_type()
242 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in realtek_gpio_irq_set_type()
243 	ctrl->intr_type[line] = type;  in realtek_gpio_irq_set_type()
245 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in realtek_gpio_irq_set_type()
261 	for_each_set_bit(offset, &status, gc->ngpio)  in realtek_gpio_irq_handler()
262 		generic_handle_domain_irq(gc->irq.domain, offset);  in realtek_gpio_irq_handler()
269 	return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu;  in realtek_gpio_irq_cpu_mask()
282 	if (!ctrl->cpumask_base)  in realtek_gpio_irq_set_affinity()
283 		return -ENXIO;  in realtek_gpio_irq_set_affinity()
285 	raw_spin_lock_irqsave(&ctrl->lock, flags);  in realtek_gpio_irq_set_affinity()
287 	for_each_cpu(cpu, &ctrl->cpu_irq_maskable) {  in realtek_gpio_irq_set_affinity()
289 		v = ctrl->bank_read(irq_cpu_mask);  in realtek_gpio_irq_set_affinity()
296 		ctrl->bank_write(irq_cpu_mask, v);  in realtek_gpio_irq_set_affinity()
299 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);  in realtek_gpio_irq_set_affinity()
309 	u32 mask_all = GENMASK(gc->ngpio - 1, 0);  in realtek_gpio_irq_init()
313 	for (line = 0; line < gc->ngpio; line++)  in realtek_gpio_irq_init()
318 	for_each_cpu(cpu, &ctrl->cpu_irq_maskable)  in realtek_gpio_irq_init()
319 		ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all);  in realtek_gpio_irq_init()
325 	.name = "realtek-otto-gpio",
337 		.compatible = "realtek,otto-gpio",
341 		.compatible = "realtek,rtl8380-gpio",
344 		.compatible = "realtek,rtl8390-gpio",
347 		.compatible = "realtek,rtl9300-gpio",
351 		.compatible = "realtek,rtl9310-gpio",
359 	struct device *dev = &pdev->dev;  in realtek_gpio_probe()
371 		return -ENOMEM;  in realtek_gpio_probe()
379 		dev_err(&pdev->dev, "invalid ngpios (max. %d)\n",  in realtek_gpio_probe()
381 		return -EINVAL;  in realtek_gpio_probe()
384 	ctrl->base = devm_platform_ioremap_resource(pdev, 0);  in realtek_gpio_probe()
385 	if (IS_ERR(ctrl->base))  in realtek_gpio_probe()
386 		return PTR_ERR(ctrl->base);  in realtek_gpio_probe()
388 	raw_spin_lock_init(&ctrl->lock);  in realtek_gpio_probe()
392 		ctrl->bank_read = realtek_gpio_bank_read;  in realtek_gpio_probe()
393 		ctrl->bank_write = realtek_gpio_bank_write;  in realtek_gpio_probe()
394 		ctrl->line_imr_pos = realtek_gpio_line_imr_pos;  in realtek_gpio_probe()
397 		ctrl->bank_read = realtek_gpio_bank_read_swapped;  in realtek_gpio_probe()
398 		ctrl->bank_write = realtek_gpio_bank_write_swapped;  in realtek_gpio_probe()
399 		ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped;  in realtek_gpio_probe()
402 	err = bgpio_init(&ctrl->gc, dev, 4,  in realtek_gpio_probe()
403 		ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,  in realtek_gpio_probe()
404 		ctrl->base + REALTEK_GPIO_REG_DIR, NULL,  in realtek_gpio_probe()
411 	ctrl->gc.ngpio = ngpios;  in realtek_gpio_probe()
412 	ctrl->gc.owner = THIS_MODULE;  in realtek_gpio_probe()
416 		girq = &ctrl->gc.irq;  in realtek_gpio_probe()
418 		girq->default_type = IRQ_TYPE_NONE;  in realtek_gpio_probe()
419 		girq->handler = handle_bad_irq;  in realtek_gpio_probe()
420 		girq->parent_handler = realtek_gpio_irq_handler;  in realtek_gpio_probe()
421 		girq->num_parents = 1;  in realtek_gpio_probe()
422 		girq->parents = devm_kcalloc(dev, girq->num_parents,  in realtek_gpio_probe()
423 					sizeof(*girq->parents),	GFP_KERNEL);  in realtek_gpio_probe()
424 		if (!girq->parents)  in realtek_gpio_probe()
425 			return -ENOMEM;  in realtek_gpio_probe()
426 		girq->parents[0] = irq;  in realtek_gpio_probe()
427 		girq->init_hw = realtek_gpio_irq_init;  in realtek_gpio_probe()
430 	cpumask_clear(&ctrl->cpu_irq_maskable);  in realtek_gpio_probe()
433 		ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);  in realtek_gpio_probe()
434 		if (IS_ERR(ctrl->cpumask_base))  in realtek_gpio_probe()
435 			return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base),  in realtek_gpio_probe()
442 			cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable);  in realtek_gpio_probe()
445 	return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);  in realtek_gpio_probe()
450 		.name = "realtek-otto-gpio",