Lines Matching +full:chip +full:- +full:to +full:- +full:chip
1 // SPDX-License-Identifier: GPL-2.0
47 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
48 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
59 * struct pch_gpio_reg_data - The register store data.
60 * @ien_reg: To store contents of IEN register.
61 * @imask_reg: To store contents of IMASK register.
62 * @po_reg: To store contents of PO register.
63 * @pm_reg: To store contents of PM register.
64 * @im0_reg: To store contents of IM0 register.
65 * @im1_reg: To store contents of IM1 register.
66 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
67 * (Only ML7223 Bus-n)
80 * struct pch_gpio - GPIO private data structure.
83 * @dev: Pointer to device structure.
105 struct pch_gpio *chip = gpiochip_get_data(gpio); in pch_gpio_set() local
108 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_set()
109 reg_val = ioread32(&chip->reg->po); in pch_gpio_set()
115 iowrite32(reg_val, &chip->reg->po); in pch_gpio_set()
116 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_set()
121 struct pch_gpio *chip = gpiochip_get_data(gpio); in pch_gpio_get() local
123 return !!(ioread32(&chip->reg->pi) & BIT(nr)); in pch_gpio_get()
129 struct pch_gpio *chip = gpiochip_get_data(gpio); in pch_gpio_direction_output() local
134 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_output()
136 reg_val = ioread32(&chip->reg->po); in pch_gpio_direction_output()
141 iowrite32(reg_val, &chip->reg->po); in pch_gpio_direction_output()
143 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_output()
144 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_output()
146 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_output()
148 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_output()
155 struct pch_gpio *chip = gpiochip_get_data(gpio); in pch_gpio_direction_input() local
159 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_direction_input()
160 pm = ioread32(&chip->reg->pm); in pch_gpio_direction_input()
161 pm &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_direction_input()
163 iowrite32(pm, &chip->reg->pm); in pch_gpio_direction_input()
164 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_direction_input()
172 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip) in pch_gpio_save_reg_conf() argument
174 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); in pch_gpio_save_reg_conf()
175 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); in pch_gpio_save_reg_conf()
176 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); in pch_gpio_save_reg_conf()
177 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); in pch_gpio_save_reg_conf()
178 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); in pch_gpio_save_reg_conf()
179 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_save_reg_conf()
180 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); in pch_gpio_save_reg_conf()
181 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_save_reg_conf()
182 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); in pch_gpio_save_reg_conf()
188 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip) in pch_gpio_restore_reg_conf() argument
190 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); in pch_gpio_restore_reg_conf()
191 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); in pch_gpio_restore_reg_conf()
192 /* to store contents of PO register */ in pch_gpio_restore_reg_conf()
193 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); in pch_gpio_restore_reg_conf()
194 /* to store contents of PM register */ in pch_gpio_restore_reg_conf()
195 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); in pch_gpio_restore_reg_conf()
196 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); in pch_gpio_restore_reg_conf()
197 if (chip->ioh == INTEL_EG20T_PCH) in pch_gpio_restore_reg_conf()
198 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); in pch_gpio_restore_reg_conf()
199 if (chip->ioh == OKISEMI_ML7223n_IOH) in pch_gpio_restore_reg_conf()
200 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); in pch_gpio_restore_reg_conf()
205 struct pch_gpio *chip = gpiochip_get_data(gpio); in pch_gpio_to_irq() local
207 return chip->irq_base + offset; in pch_gpio_to_irq()
210 static void pch_gpio_setup(struct pch_gpio *chip) in pch_gpio_setup() argument
212 struct gpio_chip *gpio = &chip->gpio; in pch_gpio_setup()
214 gpio->label = dev_name(chip->dev); in pch_gpio_setup()
215 gpio->parent = chip->dev; in pch_gpio_setup()
216 gpio->owner = THIS_MODULE; in pch_gpio_setup()
217 gpio->direction_input = pch_gpio_direction_input; in pch_gpio_setup()
218 gpio->get = pch_gpio_get; in pch_gpio_setup()
219 gpio->direction_output = pch_gpio_direction_output; in pch_gpio_setup()
220 gpio->set = pch_gpio_set; in pch_gpio_setup()
221 gpio->base = -1; in pch_gpio_setup()
222 gpio->ngpio = gpio_pins[chip->ioh]; in pch_gpio_setup()
223 gpio->can_sleep = false; in pch_gpio_setup()
224 gpio->to_irq = pch_gpio_to_irq; in pch_gpio_setup()
230 struct pch_gpio *chip = gc->private; in pch_irq_type() local
234 int ch, irq = d->irq; in pch_irq_type()
236 ch = irq - chip->irq_base; in pch_irq_type()
237 if (irq < chip->irq_base + 8) { in pch_irq_type()
238 im_reg = &chip->reg->im0; in pch_irq_type()
239 im_pos = ch - 0; in pch_irq_type()
241 im_reg = &chip->reg->im1; in pch_irq_type()
242 im_pos = ch - 8; in pch_irq_type()
244 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos); in pch_irq_type()
266 spin_lock_irqsave(&chip->spinlock, flags); in pch_irq_type()
278 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_irq_type()
285 struct pch_gpio *chip = gc->private; in pch_irq_unmask() local
287 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr); in pch_irq_unmask()
293 struct pch_gpio *chip = gc->private; in pch_irq_mask() local
295 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask); in pch_irq_mask()
301 struct pch_gpio *chip = gc->private; in pch_irq_ack() local
303 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr); in pch_irq_ack()
308 struct pch_gpio *chip = dev_id; in pch_gpio_handler() local
309 unsigned long reg_val = ioread32(&chip->reg->istatus); in pch_gpio_handler()
312 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val); in pch_gpio_handler()
314 reg_val &= BIT(gpio_pins[chip->ioh]) - 1; in pch_gpio_handler()
316 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) in pch_gpio_handler()
317 generic_handle_irq(chip->irq_base + i); in pch_gpio_handler()
322 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip, in pch_gpio_alloc_generic_chip() argument
330 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, in pch_gpio_alloc_generic_chip()
331 chip->base, handle_simple_irq); in pch_gpio_alloc_generic_chip()
333 return -ENOMEM; in pch_gpio_alloc_generic_chip()
335 gc->private = chip; in pch_gpio_alloc_generic_chip()
336 ct = gc->chip_types; in pch_gpio_alloc_generic_chip()
338 ct->chip.irq_ack = pch_irq_ack; in pch_gpio_alloc_generic_chip()
339 ct->chip.irq_mask = pch_irq_mask; in pch_gpio_alloc_generic_chip()
340 ct->chip.irq_unmask = pch_irq_unmask; in pch_gpio_alloc_generic_chip()
341 ct->chip.irq_set_type = pch_irq_type; in pch_gpio_alloc_generic_chip()
343 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), in pch_gpio_alloc_generic_chip()
353 struct device *dev = &pdev->dev; in pch_gpio_probe()
355 struct pch_gpio *chip; in pch_gpio_probe() local
358 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); in pch_gpio_probe()
359 if (chip == NULL) in pch_gpio_probe()
360 return -ENOMEM; in pch_gpio_probe()
362 chip->dev = dev; in pch_gpio_probe()
365 return dev_err_probe(dev, ret, "Failed to enable PCI device\n"); in pch_gpio_probe()
369 return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n"); in pch_gpio_probe()
371 chip->base = pcim_iomap_table(pdev)[1]; in pch_gpio_probe()
372 chip->ioh = id->driver_data; in pch_gpio_probe()
373 chip->reg = chip->base; in pch_gpio_probe()
374 pci_set_drvdata(pdev, chip); in pch_gpio_probe()
375 spin_lock_init(&chip->spinlock); in pch_gpio_probe()
376 pch_gpio_setup(chip); in pch_gpio_probe()
378 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip); in pch_gpio_probe()
380 return dev_err_probe(dev, ret, "Failed to register GPIO\n"); in pch_gpio_probe()
382 irq_base = devm_irq_alloc_descs(dev, -1, 0, in pch_gpio_probe()
383 gpio_pins[chip->ioh], NUMA_NO_NODE); in pch_gpio_probe()
385 dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n"); in pch_gpio_probe()
386 chip->irq_base = -1; in pch_gpio_probe()
389 chip->irq_base = irq_base; in pch_gpio_probe()
392 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask); in pch_gpio_probe()
393 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien); in pch_gpio_probe()
395 ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler, in pch_gpio_probe()
396 IRQF_SHARED, KBUILD_MODNAME, chip); in pch_gpio_probe()
398 return dev_err_probe(dev, ret, "Failed to request IRQ\n"); in pch_gpio_probe()
400 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); in pch_gpio_probe()
405 struct pch_gpio *chip = dev_get_drvdata(dev); in pch_gpio_suspend() local
408 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_suspend()
409 pch_gpio_save_reg_conf(chip); in pch_gpio_suspend()
410 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_suspend()
417 struct pch_gpio *chip = dev_get_drvdata(dev); in pch_gpio_resume() local
420 spin_lock_irqsave(&chip->spinlock, flags); in pch_gpio_resume()
421 iowrite32(0x01, &chip->reg->reset); in pch_gpio_resume()
422 iowrite32(0x00, &chip->reg->reset); in pch_gpio_resume()
423 pch_gpio_restore_reg_conf(chip); in pch_gpio_resume()
424 spin_unlock_irqrestore(&chip->spinlock, flags); in pch_gpio_resume()