Lines Matching +full:armada +full:- +full:xp +full:- +full:cpu +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
16 * platforms (MV78200 from the Discovery family and the Armada
17 * XP). Therefore, this driver handles three variants of the GPIO
19 * - the basic variant, called "orion-gpio", with the simplest
20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
21 * non-SMP Discovery systems
22 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * - the armadaxp variant for Armada XP systems. This variant keeps
28 * interrupts are used, but adds per-CPU cause/edge mask/level mask
29 * registers n a separate memory area for the per-CPU GPIO
74 /* Armada 8k variant gpios register offsets */
79 /* The MV78200 has per-CPU registers for edge mask and level mask */
80 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) argument
81 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) argument
84 * The Armada XP has per-CPU registers for interrupt cause, interrupt
87 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) argument
88 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) argument
89 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) argument
142 int cpu; in mvebu_gpioreg_edge_cause() local
144 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_cause()
148 *map = mvchip->regs; in mvebu_gpioreg_edge_cause()
149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; in mvebu_gpioreg_edge_cause()
152 cpu = smp_processor_id(); in mvebu_gpioreg_edge_cause()
153 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_cause()
154 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_cause()
188 int cpu; in mvebu_gpioreg_edge_mask() local
190 switch (mvchip->soc_variant) { in mvebu_gpioreg_edge_mask()
193 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; in mvebu_gpioreg_edge_mask()
197 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
198 *map = mvchip->regs; in mvebu_gpioreg_edge_mask()
199 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_edge_mask()
202 cpu = smp_processor_id(); in mvebu_gpioreg_edge_mask()
203 *map = mvchip->percpu_regs; in mvebu_gpioreg_edge_mask()
204 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_edge_mask()
238 int cpu; in mvebu_gpioreg_level_mask() local
240 switch (mvchip->soc_variant) { in mvebu_gpioreg_level_mask()
243 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; in mvebu_gpioreg_level_mask()
247 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
248 *map = mvchip->regs; in mvebu_gpioreg_level_mask()
249 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); in mvebu_gpioreg_level_mask()
252 cpu = smp_processor_id(); in mvebu_gpioreg_level_mask()
253 *map = mvchip->percpu_regs; in mvebu_gpioreg_level_mask()
254 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); in mvebu_gpioreg_level_mask()
290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; in mvebu_pwmreg_blink_on_duration()
295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; in mvebu_pwmreg_blink_off_duration()
305 return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_set()
314 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get()
319 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, in mvebu_gpio_get()
321 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_get()
325 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); in mvebu_gpio_get()
336 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_blink()
353 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_input()
376 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_direction_output()
387 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_get_direction()
399 return irq_create_mapping(mvchip->domain, pin); in mvebu_gpio_to_irq()
408 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_ack()
409 u32 mask = d->mask; in mvebu_gpio_irq_ack()
411 guard(raw_spinlock)(&gc->lock); in mvebu_gpio_irq_ack()
418 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_mask()
420 u32 mask = d->mask; in mvebu_gpio_edge_irq_mask()
422 guard(raw_spinlock)(&gc->lock); in mvebu_gpio_edge_irq_mask()
423 ct->mask_cache_priv &= ~mask; in mvebu_gpio_edge_irq_mask()
424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_mask()
430 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_edge_irq_unmask()
432 u32 mask = d->mask; in mvebu_gpio_edge_irq_unmask()
434 guard(raw_spinlock)(&gc->lock); in mvebu_gpio_edge_irq_unmask()
436 ct->mask_cache_priv |= mask; in mvebu_gpio_edge_irq_unmask()
437 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_edge_irq_unmask()
443 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_mask()
445 u32 mask = d->mask; in mvebu_gpio_level_irq_mask()
447 guard(raw_spinlock)(&gc->lock); in mvebu_gpio_level_irq_mask()
448 ct->mask_cache_priv &= ~mask; in mvebu_gpio_level_irq_mask()
449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_mask()
455 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_level_irq_unmask()
457 u32 mask = d->mask; in mvebu_gpio_level_irq_unmask()
459 guard(raw_spinlock)(&gc->lock); in mvebu_gpio_level_irq_unmask()
460 ct->mask_cache_priv |= mask; in mvebu_gpio_level_irq_unmask()
461 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); in mvebu_gpio_level_irq_unmask()
474 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
483 * data-in /--------| |-----| |----\
484 * -----| |----- ---- to main cause reg
485 * X \----------------| |----/
494 struct mvebu_gpio_chip *mvchip = gc->private; in mvebu_gpio_irq_set_type()
498 pin = d->hwirq; in mvebu_gpio_irq_set_type()
500 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); in mvebu_gpio_irq_set_type()
502 return -EINVAL; in mvebu_gpio_irq_set_type()
506 return -EINVAL; in mvebu_gpio_irq_set_type()
509 if (!(ct->type & type)) in mvebu_gpio_irq_set_type()
511 return -EINVAL; in mvebu_gpio_irq_set_type()
519 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
520 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
525 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
526 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
532 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
533 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_irq_set_type()
534 regmap_read(mvchip->regs, in mvebu_gpio_irq_set_type()
535 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_set_type()
545 regmap_update_bits(mvchip->regs, in mvebu_gpio_irq_set_type()
546 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_set_type()
566 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_irq_handler()
573 for (i = 0; i < mvchip->chip.ngpio; i++) { in mvebu_gpio_irq_handler()
576 irq = irq_find_mapping(mvchip->domain, i); in mvebu_gpio_irq_handler()
586 regmap_read(mvchip->regs, in mvebu_gpio_irq_handler()
587 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
590 regmap_write(mvchip->regs, in mvebu_gpio_irq_handler()
591 GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_irq_handler()
619 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_request()
624 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_request()
626 if (mvpwm->gpiod) { in mvebu_pwm_request()
627 ret = -EBUSY; in mvebu_pwm_request()
629 desc = gpiochip_request_own_desc(&mvchip->chip, in mvebu_pwm_request()
630 pwm->hwpwm, "mvebu-pwm", in mvebu_pwm_request()
638 mvpwm->gpiod = desc; in mvebu_pwm_request()
641 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_request()
650 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_free()
651 gpiochip_free_own_desc(mvpwm->gpiod); in mvebu_pwm_free()
652 mvpwm->gpiod = NULL; in mvebu_pwm_free()
653 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_free()
662 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_get_state()
667 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_get_state()
669 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); in mvebu_pwm_get_state()
675 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, in mvebu_pwm_get_state()
676 mvpwm->clk_rate); in mvebu_pwm_get_state()
678 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); in mvebu_pwm_get_state()
684 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); in mvebu_pwm_get_state()
686 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); in mvebu_pwm_get_state()
688 state->enabled = true; in mvebu_pwm_get_state()
690 state->enabled = false; in mvebu_pwm_get_state()
692 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_get_state()
701 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; in mvebu_pwm_apply()
706 if (state->polarity != PWM_POLARITY_NORMAL) in mvebu_pwm_apply()
707 return -EINVAL; in mvebu_pwm_apply()
709 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; in mvebu_pwm_apply()
712 return -EINVAL; in mvebu_pwm_apply()
724 val = (unsigned long long) mvpwm->clk_rate * state->period; in mvebu_pwm_apply()
726 val -= on; in mvebu_pwm_apply()
728 return -EINVAL; in mvebu_pwm_apply()
736 spin_lock_irqsave(&mvpwm->lock, flags); in mvebu_pwm_apply()
738 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); in mvebu_pwm_apply()
739 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); in mvebu_pwm_apply()
740 if (state->enabled) in mvebu_pwm_apply()
741 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); in mvebu_pwm_apply()
743 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); in mvebu_pwm_apply()
745 spin_unlock_irqrestore(&mvpwm->lock, flags); in mvebu_pwm_apply()
759 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_suspend()
761 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_suspend()
762 &mvpwm->blink_select); in mvebu_pwm_suspend()
763 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_suspend()
764 &mvpwm->blink_on_duration); in mvebu_pwm_suspend()
765 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_suspend()
766 &mvpwm->blink_off_duration); in mvebu_pwm_suspend()
771 struct mvebu_pwm *mvpwm = mvchip->mvpwm; in mvebu_pwm_resume()
773 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, in mvebu_pwm_resume()
774 mvpwm->blink_select); in mvebu_pwm_resume()
775 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), in mvebu_pwm_resume()
776 mvpwm->blink_on_duration); in mvebu_pwm_resume()
777 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), in mvebu_pwm_resume()
778 mvpwm->blink_off_duration); in mvebu_pwm_resume()
785 struct device *dev = &pdev->dev; in mvebu_pwm_probe()
792 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
793 int ret = device_property_read_u32(dev, "marvell,pwm-offset", in mvebu_pwm_probe()
809 if (IS_ERR(mvchip->clk)) in mvebu_pwm_probe()
810 return PTR_ERR(mvchip->clk); in mvebu_pwm_probe()
812 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm)); in mvebu_pwm_probe()
817 mvchip->mvpwm = mvpwm; in mvebu_pwm_probe()
818 mvpwm->mvchip = mvchip; in mvebu_pwm_probe()
819 mvpwm->offset = offset; in mvebu_pwm_probe()
821 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { in mvebu_pwm_probe()
822 mvpwm->regs = mvchip->regs; in mvebu_pwm_probe()
824 switch (mvchip->offset) { in mvebu_pwm_probe()
833 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; in mvebu_pwm_probe()
836 return -EINVAL; in mvebu_pwm_probe()
843 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_pwm_probe()
845 if (IS_ERR(mvpwm->regs)) in mvebu_pwm_probe()
846 return PTR_ERR(mvpwm->regs); in mvebu_pwm_probe()
857 return -EINVAL; in mvebu_pwm_probe()
860 regmap_write(mvchip->regs, in mvebu_pwm_probe()
861 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); in mvebu_pwm_probe()
863 mvpwm->clk_rate = clk_get_rate(mvchip->clk); in mvebu_pwm_probe()
864 if (!mvpwm->clk_rate) { in mvebu_pwm_probe()
865 dev_err(dev, "failed to get clock rate\n"); in mvebu_pwm_probe()
866 return -EINVAL; in mvebu_pwm_probe()
869 chip->ops = &mvebu_pwm_ops; in mvebu_pwm_probe()
871 spin_lock_init(&mvpwm->lock); in mvebu_pwm_probe()
886 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); in mvebu_gpio_dbg_show()
887 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); in mvebu_gpio_dbg_show()
888 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); in mvebu_gpio_dbg_show()
889 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); in mvebu_gpio_dbg_show()
890 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); in mvebu_gpio_dbg_show()
902 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); in mvebu_gpio_dbg_show()
911 seq_printf(s, " in %s (act %s) - IRQ", in mvebu_gpio_dbg_show()
931 .compatible = "marvell,orion-gpio",
935 .compatible = "marvell,mv78200-gpio",
939 .compatible = "marvell,armadaxp-gpio",
943 .compatible = "marvell,armada-370-gpio",
947 .compatible = "marvell,armada-8k-gpio",
960 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_suspend()
961 &mvchip->out_reg); in mvebu_gpio_suspend()
962 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_suspend()
963 &mvchip->io_conf_reg); in mvebu_gpio_suspend()
964 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_suspend()
965 &mvchip->blink_en_reg); in mvebu_gpio_suspend()
966 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_suspend()
967 &mvchip->in_pol_reg); in mvebu_gpio_suspend()
969 switch (mvchip->soc_variant) { in mvebu_gpio_suspend()
972 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
973 &mvchip->edge_mask_regs[0]); in mvebu_gpio_suspend()
974 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_suspend()
975 &mvchip->level_mask_regs[0]); in mvebu_gpio_suspend()
979 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
981 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
982 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
984 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
989 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
991 &mvchip->edge_mask_regs[i]); in mvebu_gpio_suspend()
992 regmap_read(mvchip->regs, in mvebu_gpio_suspend()
994 &mvchip->level_mask_regs[i]); in mvebu_gpio_suspend()
1012 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, in mvebu_gpio_resume()
1013 mvchip->out_reg); in mvebu_gpio_resume()
1014 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, in mvebu_gpio_resume()
1015 mvchip->io_conf_reg); in mvebu_gpio_resume()
1016 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, in mvebu_gpio_resume()
1017 mvchip->blink_en_reg); in mvebu_gpio_resume()
1018 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, in mvebu_gpio_resume()
1019 mvchip->in_pol_reg); in mvebu_gpio_resume()
1021 switch (mvchip->soc_variant) { in mvebu_gpio_resume()
1024 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1025 mvchip->edge_mask_regs[0]); in mvebu_gpio_resume()
1026 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, in mvebu_gpio_resume()
1027 mvchip->level_mask_regs[0]); in mvebu_gpio_resume()
1031 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1033 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1034 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1036 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1041 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1043 mvchip->edge_mask_regs[i]); in mvebu_gpio_resume()
1044 regmap_write(mvchip->regs, in mvebu_gpio_resume()
1046 mvchip->level_mask_regs[i]); in mvebu_gpio_resume()
1068 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1070 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_raw()
1071 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_raw()
1077 mvchip->offset = 0; in mvebu_gpio_probe_raw()
1080 * The Armada XP has a second range of registers for the in mvebu_gpio_probe_raw()
1081 * per-CPU registers in mvebu_gpio_probe_raw()
1083 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { in mvebu_gpio_probe_raw()
1088 mvchip->percpu_regs = in mvebu_gpio_probe_raw()
1089 devm_regmap_init_mmio(&pdev->dev, base, in mvebu_gpio_probe_raw()
1091 if (IS_ERR(mvchip->percpu_regs)) in mvebu_gpio_probe_raw()
1092 return PTR_ERR(mvchip->percpu_regs); in mvebu_gpio_probe_raw()
1101 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); in mvebu_gpio_probe_syscon()
1102 if (IS_ERR(mvchip->regs)) in mvebu_gpio_probe_syscon()
1103 return PTR_ERR(mvchip->regs); in mvebu_gpio_probe_syscon()
1105 if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset)) in mvebu_gpio_probe_syscon()
1106 return -EINVAL; in mvebu_gpio_probe_syscon()
1121 struct device_node *np = pdev->dev.of_node; in mvebu_gpio_probe()
1127 int i, cpu, id; in mvebu_gpio_probe() local
1130 soc_variant = (unsigned long)device_get_match_data(&pdev->dev); in mvebu_gpio_probe()
1139 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), in mvebu_gpio_probe()
1142 return -ENOMEM; in mvebu_gpio_probe()
1146 if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) { in mvebu_gpio_probe()
1147 dev_err(&pdev->dev, "Missing ngpios OF property\n"); in mvebu_gpio_probe()
1148 return -ENODEV; in mvebu_gpio_probe()
1151 id = of_alias_get_id(pdev->dev.of_node, "gpio"); in mvebu_gpio_probe()
1153 dev_err(&pdev->dev, "Couldn't get OF id\n"); in mvebu_gpio_probe()
1157 mvchip->clk = devm_clk_get(&pdev->dev, NULL); in mvebu_gpio_probe()
1158 /* Not all SoCs require a clock.*/ in mvebu_gpio_probe()
1159 if (!IS_ERR(mvchip->clk)) in mvebu_gpio_probe()
1160 clk_prepare_enable(mvchip->clk); in mvebu_gpio_probe()
1162 mvchip->soc_variant = soc_variant; in mvebu_gpio_probe()
1163 mvchip->chip.label = dev_name(&pdev->dev); in mvebu_gpio_probe()
1164 mvchip->chip.parent = &pdev->dev; in mvebu_gpio_probe()
1165 mvchip->chip.request = gpiochip_generic_request; in mvebu_gpio_probe()
1166 mvchip->chip.free = gpiochip_generic_free; in mvebu_gpio_probe()
1167 mvchip->chip.get_direction = mvebu_gpio_get_direction; in mvebu_gpio_probe()
1168 mvchip->chip.direction_input = mvebu_gpio_direction_input; in mvebu_gpio_probe()
1169 mvchip->chip.get = mvebu_gpio_get; in mvebu_gpio_probe()
1170 mvchip->chip.direction_output = mvebu_gpio_direction_output; in mvebu_gpio_probe()
1171 mvchip->chip.set = mvebu_gpio_set; in mvebu_gpio_probe()
1173 mvchip->chip.to_irq = mvebu_gpio_to_irq; in mvebu_gpio_probe()
1174 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; in mvebu_gpio_probe()
1175 mvchip->chip.ngpio = ngpios; in mvebu_gpio_probe()
1176 mvchip->chip.can_sleep = false; in mvebu_gpio_probe()
1177 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; in mvebu_gpio_probe()
1193 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1194 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1195 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1196 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1197 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1198 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); in mvebu_gpio_probe()
1201 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1202 for (cpu = 0; cpu < 2; cpu++) { in mvebu_gpio_probe()
1203 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1204 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1205 regmap_write(mvchip->regs, in mvebu_gpio_probe()
1206 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); in mvebu_gpio_probe()
1210 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); in mvebu_gpio_probe()
1211 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); in mvebu_gpio_probe()
1212 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); in mvebu_gpio_probe()
1213 for (cpu = 0; cpu < 4; cpu++) { in mvebu_gpio_probe()
1214 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1215 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1216 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1217 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1218 regmap_write(mvchip->percpu_regs, in mvebu_gpio_probe()
1219 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); in mvebu_gpio_probe()
1226 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); in mvebu_gpio_probe()
1239 mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios, in mvebu_gpio_probe()
1241 if (!mvchip->domain) { in mvebu_gpio_probe()
1242 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", in mvebu_gpio_probe()
1243 mvchip->chip.label); in mvebu_gpio_probe()
1244 return -ENODEV; in mvebu_gpio_probe()
1247 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, in mvebu_gpio_probe()
1248 mvchip->domain); in mvebu_gpio_probe()
1253 mvchip->domain, ngpios, 2, np->name, handle_level_irq, in mvebu_gpio_probe()
1256 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", in mvebu_gpio_probe()
1257 mvchip->chip.label); in mvebu_gpio_probe()
1265 gc = irq_get_domain_generic_chip(mvchip->domain, 0); in mvebu_gpio_probe()
1266 gc->private = mvchip; in mvebu_gpio_probe()
1267 ct = &gc->chip_types[0]; in mvebu_gpio_probe()
1268 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; in mvebu_gpio_probe()
1269 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; in mvebu_gpio_probe()
1270 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; in mvebu_gpio_probe()
1271 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1272 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1274 ct = &gc->chip_types[1]; in mvebu_gpio_probe()
1275 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; in mvebu_gpio_probe()
1276 ct->chip.irq_ack = mvebu_gpio_irq_ack; in mvebu_gpio_probe()
1277 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; in mvebu_gpio_probe()
1278 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; in mvebu_gpio_probe()
1279 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; in mvebu_gpio_probe()
1280 ct->handler = handle_edge_irq; in mvebu_gpio_probe()
1281 ct->chip.name = mvchip->chip.label; in mvebu_gpio_probe()
1302 .name = "mvebu-gpio",