Lines Matching +full:gpio +full:- +full:line
1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic driver for memory-mapped GPIO controllers.
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
59 #include <linux/gpio/driver.h>
125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
127 if (gc->be_bits)
128 return BIT(gc->bgpio_bits - 1 - line);
129 return BIT(line);
132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
134 unsigned long pinmask = bgpio_line2mask(gc, gpio);
135 bool dir = !!(gc->bgpio_dir & pinmask);
138 return !!(gc->read_reg(gc->reg_set) & pinmask);
140 return !!(gc->read_reg(gc->reg_dat) & pinmask);
144 * This assumes that the bits in the GPIO register are in native endianness.
156 set_mask = *mask & gc->bgpio_dir;
157 get_mask = *mask & ~gc->bgpio_dir;
160 *bits |= gc->read_reg(gc->reg_set) & set_mask;
162 *bits |= gc->read_reg(gc->reg_dat) & get_mask;
167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
173 * This only works if the bits in the GPIO register are in native endianness.
180 *bits |= gc->read_reg(gc->reg_dat) & *mask;
198 for_each_set_bit(bit, mask, gc->ngpio)
202 val = gc->read_reg(gc->reg_dat) & readmask;
205 * Mirror the result into the "bits" result, this will give line 0
206 * in bit 0 ... line 31 in bit 31 for a 32bit register.
208 for_each_set_bit(bit, &val, gc->ngpio)
214 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
218 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
220 unsigned long mask = bgpio_line2mask(gc, gpio);
223 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
226 gc->bgpio_data |= mask;
228 gc->bgpio_data &= ~mask;
230 gc->write_reg(gc->reg_dat, gc->bgpio_data);
232 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
238 unsigned long mask = bgpio_line2mask(gc, gpio);
241 gc->write_reg(gc->reg_set, mask);
243 gc->write_reg(gc->reg_clr, mask);
246 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
248 unsigned long mask = bgpio_line2mask(gc, gpio);
251 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
254 gc->bgpio_data |= mask;
256 gc->bgpio_data &= ~mask;
258 gc->write_reg(gc->reg_set, gc->bgpio_data);
260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
273 for_each_set_bit(i, mask, gc->bgpio_bits) {
289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
293 gc->bgpio_data |= set_mask;
294 gc->bgpio_data &= ~clear_mask;
296 gc->write_reg(reg, gc->bgpio_data);
298 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
304 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
310 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
322 gc->write_reg(gc->reg_set, set_mask);
324 gc->write_reg(gc->reg_clr, clear_mask);
327 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out)
329 if (!gc->bgpio_pinctrl)
333 return pinctrl_gpio_direction_output(gc, gpio);
335 return pinctrl_gpio_direction_input(gc, gpio);
338 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
340 return bgpio_dir_return(gc, gpio, false);
343 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
346 return -EINVAL;
349 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
352 gc->set(gc, gpio, val);
354 return bgpio_dir_return(gc, gpio, true);
357 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
361 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
363 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
365 if (gc->reg_dir_in)
366 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
367 if (gc->reg_dir_out)
368 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
370 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
372 return bgpio_dir_return(gc, gpio, false);
375 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
378 if (gc->bgpio_dir_unreadable) {
379 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
384 if (gc->reg_dir_out) {
385 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
390 if (gc->reg_dir_in)
391 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
397 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
401 raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
403 gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
405 if (gc->reg_dir_in)
406 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
407 if (gc->reg_dir_out)
408 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
410 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
413 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
416 bgpio_dir_out(gc, gpio, val);
417 gc->set(gc, gpio, val);
418 return bgpio_dir_return(gc, gpio, true);
421 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
424 gc->set(gc, gpio, val);
425 bgpio_dir_out(gc, gpio, val);
426 return bgpio_dir_return(gc, gpio, true);
434 switch (gc->bgpio_bits) {
436 gc->read_reg = bgpio_read8;
437 gc->write_reg = bgpio_write8;
441 gc->read_reg = bgpio_read16be;
442 gc->write_reg = bgpio_write16be;
444 gc->read_reg = bgpio_read16;
445 gc->write_reg = bgpio_write16;
450 gc->read_reg = bgpio_read32be;
451 gc->write_reg = bgpio_write32be;
453 gc->read_reg = bgpio_read32;
454 gc->write_reg = bgpio_write32;
462 return -EINVAL;
464 gc->read_reg = bgpio_read64;
465 gc->write_reg = bgpio_write64;
470 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
471 return -EINVAL;
478 * Create the device and allocate the resources. For setting GPIO's there are
481 * - single input/output register resource (named "dat").
482 * - set/clear pair (named "set" and "clr").
483 * - single output register resource and single input resource ("set" and
491 * For setting the GPIO direction, there are three supported configurations:
493 * - simple bidirection GPIO that requires no configuration.
494 * - an output direction register (named "dirout") where a 1 bit
495 * indicates the GPIO is an output.
496 * - an input direction register (named "dirin") where a 1 bit indicates
497 * the GPIO is an input.
506 gc->reg_dat = dat;
507 if (!gc->reg_dat)
508 return -EINVAL;
511 gc->reg_set = set;
512 gc->reg_clr = clr;
513 gc->set = bgpio_set_with_clear;
514 gc->set_multiple = bgpio_set_multiple_with_clear;
516 gc->reg_set = set;
517 gc->set = bgpio_set_set;
518 gc->set_multiple = bgpio_set_multiple_set;
520 gc->set = bgpio_set_none;
521 gc->set_multiple = NULL;
523 gc->set = bgpio_set;
524 gc->set_multiple = bgpio_set_multiple;
529 gc->get = bgpio_get_set;
530 if (!gc->be_bits)
531 gc->get_multiple = bgpio_get_set_multiple;
533 * We deliberately avoid assigning the ->get_multiple() call
536 * simply too much complexity, let the GPIO core fall back to
537 * reading each line individually in that fringe case.
540 gc->get = bgpio_get;
541 if (gc->be_bits)
542 gc->get_multiple = bgpio_get_multiple_be;
544 gc->get_multiple = bgpio_get_multiple;
556 gc->reg_dir_out = dirout;
557 gc->reg_dir_in = dirin;
559 gc->direction_output = bgpio_dir_out_dir_first;
561 gc->direction_output = bgpio_dir_out_val_first;
562 gc->direction_input = bgpio_dir_in;
563 gc->get_direction = bgpio_get_dir;
566 gc->direction_output = bgpio_dir_out_err;
568 gc->direction_output = bgpio_simple_dir_out;
569 gc->direction_input = bgpio_simple_dir_in;
577 if (gpio_pin >= chip->ngpio)
578 return -EINVAL;
580 if (chip->bgpio_pinctrl)
587 * bgpio_init() - Initialize generic GPIO accessor functions
588 * @gc: the GPIO chip to set up
589 * @dev: the parent device of the new GPIO chip (compulsory)
591 * @dat: MMIO address for the register to READ the value of the GPIO lines, it
593 * line is asserted
594 * @set: MMIO address for the register to SET the value of the GPIO lines, it is
595 * expected that we write the line with 1 in this register to drive the GPIO line
597 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
598 * expected that we write the line with 1 in this register to drive the GPIO line
600 * will be assumed to also clear the GPIO lines, by actively writing the line
602 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
603 * that setting a line to 1 in this register will turn that line into an
604 * output line. Conversely, setting the line to 0 will turn that line into
606 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
607 * that setting a line to 1 in this register will turn that line into an
608 * input line. Conversely, setting the line to 0 will turn that line into
621 return -EINVAL;
623 gc->bgpio_bits = sz * 8;
624 if (gc->bgpio_bits > BITS_PER_LONG)
625 return -EINVAL;
627 raw_spin_lock_init(&gc->bgpio_lock);
628 gc->parent = dev;
629 gc->label = dev_name(dev);
630 gc->base = -1;
631 gc->request = bgpio_request;
632 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
636 gc->ngpio = gc->bgpio_bits;
651 gc->bgpio_pinctrl = true;
653 gc->free = gpiochip_generic_free;
656 gc->bgpio_data = gc->read_reg(gc->reg_dat);
657 if (gc->set == bgpio_set_set &&
659 gc->bgpio_data = gc->read_reg(gc->reg_set);
662 gc->bgpio_dir_unreadable = true;
667 if ((gc->reg_dir_out || gc->reg_dir_in) &&
669 if (gc->reg_dir_out)
670 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
671 else if (gc->reg_dir_in)
672 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
676 * can not handle a line being input and output at
679 if (gc->reg_dir_out && gc->reg_dir_in)
680 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
702 return IOMEM_ERR_PTR(-EINVAL);
704 return devm_ioremap_resource(&pdev->dev, r);
708 { .compatible = "brcm,bcm6345-gpio" },
709 { .compatible = "wd,mbl-gpio" },
710 { .compatible = "ni,169445-nand-gpio" },
724 return ERR_PTR(-ENOMEM);
726 pdata->base = -1;
731 if (device_property_read_bool(dev, "no-output"))
739 struct device *dev = &pdev->dev;
758 flags = pdev->id_entry->driver_data;
763 return -EINVAL;
787 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
789 return -ENOMEM;
796 if (pdata->label)
797 gc->label = pdata->label;
798 gc->base = pdata->base;
799 if (pdata->ngpio > 0)
800 gc->ngpio = pdata->ngpio;
805 return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
810 .name = "basic-mmio-gpio",
813 .name = "basic-mmio-gpio-be",
822 .name = "basic-mmio-gpio",
833 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");