1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/gpio/driver.h>
24 #include "gpiolib-acpi.h"
46 #define DWAPB_DRIVER_NAME	"gpio-dwapb"
82 /* Store GPIO context across system-wide suspend/resume transitions */
104 	struct dwapb_gpio	*gpio;  member
111 	(container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
141 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)  in gpio_reg_convert()  argument
143 	if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)  in gpio_reg_convert()
149 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)  in dwapb_read()  argument
151 	struct gpio_chip *gc	= &gpio->ports[0].gc;  in dwapb_read()
152 	void __iomem *reg_base	= gpio->regs;  in dwapb_read()
154 	return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));  in dwapb_read()
157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,  in dwapb_write()  argument
160 	struct gpio_chip *gc	= &gpio->ports[0].gc;  in dwapb_write()
161 	void __iomem *reg_base	= gpio->regs;  in dwapb_write()
163 	gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);  in dwapb_write()
166 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)  in dwapb_offs_to_port()  argument
171 	for (i = 0; i < gpio->nr_ports; i++) {  in dwapb_offs_to_port()
172 		port = &gpio->ports[i];  in dwapb_offs_to_port()
173 		if (port->idx == offs / DWAPB_MAX_GPIOS)  in dwapb_offs_to_port()
180 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)  in dwapb_toggle_trigger()  argument
182 	struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);  in dwapb_toggle_trigger()
189 	gc = &port->gc;  in dwapb_toggle_trigger()
191 	pol = dwapb_read(gpio, GPIO_INT_POLARITY);  in dwapb_toggle_trigger()
193 	val = gc->get(gc, offs % DWAPB_MAX_GPIOS);  in dwapb_toggle_trigger()
199 	dwapb_write(gpio, GPIO_INT_POLARITY, pol);  in dwapb_toggle_trigger()
202 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)  in dwapb_do_irq()  argument
204 	struct gpio_chip *gc = &gpio->ports[0].gc;  in dwapb_do_irq()
208 	irq_status = dwapb_read(gpio, GPIO_INTSTATUS);  in dwapb_do_irq()
210 		int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);  in dwapb_do_irq()
216 			dwapb_toggle_trigger(gpio, hwirq);  in dwapb_do_irq()
224 	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);  in dwapb_irq_handler()  local
228 	dwapb_do_irq(gpio);  in dwapb_irq_handler()
240 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_ack()  local
244 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_ack()
245 	dwapb_write(gpio, GPIO_PORTA_EOI, val);  in dwapb_irq_ack()
246 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_ack()
252 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_mask()  local
257 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_mask()
258 	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);  in dwapb_irq_mask()
259 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_mask()
260 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_mask()
268 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_unmask()  local
275 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_unmask()
276 	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);  in dwapb_irq_unmask()
277 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_unmask()
278 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_unmask()
284 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_enable()  local
289 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_enable()
290 	val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);  in dwapb_irq_enable()
291 	dwapb_write(gpio, GPIO_INTEN, val);  in dwapb_irq_enable()
292 	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);  in dwapb_irq_enable()
293 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_enable()
294 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_enable()
300 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_disable()  local
305 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_disable()
306 	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);  in dwapb_irq_disable()
307 	dwapb_write(gpio, GPIO_INTMASK, val);  in dwapb_irq_disable()
308 	val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);  in dwapb_irq_disable()
309 	dwapb_write(gpio, GPIO_INTEN, val);  in dwapb_irq_disable()
310 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_disable()
316 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_set_type()  local
320 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_irq_set_type()
321 	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);  in dwapb_irq_set_type()
322 	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);  in dwapb_irq_set_type()
327 		dwapb_toggle_trigger(gpio, bit);  in dwapb_irq_set_type()
352 	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);  in dwapb_irq_set_type()
354 		dwapb_write(gpio, GPIO_INT_POLARITY, polarity);  in dwapb_irq_set_type()
355 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_irq_set_type()
364 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);  in dwapb_irq_set_wake()  local
365 	struct dwapb_context *ctx = gpio->ports[0].ctx;  in dwapb_irq_set_wake()
369 		ctx->wake_en |= BIT(bit);  in dwapb_irq_set_wake()
371 		ctx->wake_en &= ~BIT(bit);  in dwapb_irq_set_wake()
396 	struct dwapb_gpio *gpio = port->gpio;  in dwapb_gpio_set_debounce()  local
400 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_gpio_set_debounce()
402 	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);  in dwapb_gpio_set_debounce()
407 	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);  in dwapb_gpio_set_debounce()
409 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_gpio_set_debounce()
433 	for (i = 0; i < pp->ngpio; ++i) {  in dwapb_convert_irqs()
434 		if (!pp->irq[i])  in dwapb_convert_irqs()
437 		pirq->irq[pirq->nr_irqs++] = pp->irq[i];  in dwapb_convert_irqs()
440 	return pirq->nr_irqs ? 0 : -ENOENT;  in dwapb_convert_irqs()
443 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,  in dwapb_configure_irqs()  argument
448 	struct gpio_chip *gc = &port->gc;  in dwapb_configure_irqs()
452 	pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);  in dwapb_configure_irqs()
457 		dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);  in dwapb_configure_irqs()
461 	girq = &gc->irq;  in dwapb_configure_irqs()
462 	girq->handler = handle_bad_irq;  in dwapb_configure_irqs()
463 	girq->default_type = IRQ_TYPE_NONE;  in dwapb_configure_irqs()
465 	port->pirq = pirq;  in dwapb_configure_irqs()
468 	 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO  in dwapb_configure_irqs()
473 	if (has_acpi_companion(gpio->dev)) {  in dwapb_configure_irqs()
474 		girq->num_parents = 0;  in dwapb_configure_irqs()
475 		girq->parents = NULL;  in dwapb_configure_irqs()
476 		girq->parent_handler = NULL;  in dwapb_configure_irqs()
478 		err = devm_request_irq(gpio->dev, pp->irq[0],  in dwapb_configure_irqs()
480 				       IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);  in dwapb_configure_irqs()
482 			dev_err(gpio->dev, "error requesting IRQ\n");  in dwapb_configure_irqs()
486 		girq->num_parents = pirq->nr_irqs;  in dwapb_configure_irqs()
487 		girq->parents = pirq->irq;  in dwapb_configure_irqs()
488 		girq->parent_handler_data = gpio;  in dwapb_configure_irqs()
489 		girq->parent_handler = dwapb_irq_handler;  in dwapb_configure_irqs()
497 	devm_kfree(gpio->dev, pirq);  in dwapb_configure_irqs()
500 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,  in dwapb_gpio_add_port()  argument
508 	port = &gpio->ports[offs];  in dwapb_gpio_add_port()
509 	port->gpio = gpio;  in dwapb_gpio_add_port()
510 	port->idx = pp->idx;  in dwapb_gpio_add_port()
513 	port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);  in dwapb_gpio_add_port()
514 	if (!port->ctx)  in dwapb_gpio_add_port()
515 		return -ENOMEM;  in dwapb_gpio_add_port()
518 	dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;  in dwapb_gpio_add_port()
519 	set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;  in dwapb_gpio_add_port()
520 	dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;  in dwapb_gpio_add_port()
522 	/* This registers 32 GPIO lines per port */  in dwapb_gpio_add_port()
523 	err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,  in dwapb_gpio_add_port()
526 		dev_err(gpio->dev, "failed to init gpio chip for port%d\n",  in dwapb_gpio_add_port()
527 			port->idx);  in dwapb_gpio_add_port()
531 	port->gc.fwnode = pp->fwnode;  in dwapb_gpio_add_port()
532 	port->gc.ngpio = pp->ngpio;  in dwapb_gpio_add_port()
533 	port->gc.base = pp->gpio_base;  in dwapb_gpio_add_port()
534 	port->gc.request = gpiochip_generic_request;  in dwapb_gpio_add_port()
535 	port->gc.free = gpiochip_generic_free;  in dwapb_gpio_add_port()
538 	if (pp->idx == 0)  in dwapb_gpio_add_port()
539 		port->gc.set_config = dwapb_gpio_set_config;  in dwapb_gpio_add_port()
541 		port->gc.set_config = gpiochip_generic_config;  in dwapb_gpio_add_port()
544 	if (pp->idx == 0)  in dwapb_gpio_add_port()
545 		dwapb_configure_irqs(gpio, port, pp);  in dwapb_gpio_add_port()
547 	err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);  in dwapb_gpio_add_port()
549 		dev_err(gpio->dev, "failed to register gpiochip for port%d\n",  in dwapb_gpio_add_port()
550 			port->idx);  in dwapb_gpio_add_port()
562 	for (j = 0; j < pp->ngpio; j++) {  in dwapb_get_irq()
568 			pp->irq[j] = irq;  in dwapb_get_irq()
582 		return ERR_PTR(-ENODEV);  in dwapb_gpio_get_pdata()
586 		return ERR_PTR(-ENOMEM);  in dwapb_gpio_get_pdata()
588 	pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);  in dwapb_gpio_get_pdata()
589 	if (!pdata->properties)  in dwapb_gpio_get_pdata()
590 		return ERR_PTR(-ENOMEM);  in dwapb_gpio_get_pdata()
592 	pdata->nports = nports;  in dwapb_gpio_get_pdata()
596 		pp = &pdata->properties[i++];  in dwapb_gpio_get_pdata()
597 		pp->fwnode = fwnode;  in dwapb_gpio_get_pdata()
599 		if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||  in dwapb_gpio_get_pdata()
600 		    pp->idx >= DWAPB_MAX_PORTS) {  in dwapb_gpio_get_pdata()
604 			return ERR_PTR(-EINVAL);  in dwapb_gpio_get_pdata()
607 		if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&  in dwapb_gpio_get_pdata()
608 		    fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {  in dwapb_gpio_get_pdata()
612 			pp->ngpio = DWAPB_MAX_GPIOS;  in dwapb_gpio_get_pdata()
615 		pp->gpio_base	= -1;  in dwapb_gpio_get_pdata()
619 			fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);  in dwapb_gpio_get_pdata()
625 		if (pp->idx == 0)  in dwapb_gpio_get_pdata()
634 	struct dwapb_gpio *gpio = data;  in dwapb_assert_reset()  local
636 	reset_control_assert(gpio->rst);  in dwapb_assert_reset()
639 static int dwapb_get_reset(struct dwapb_gpio *gpio)  in dwapb_get_reset()  argument
643 	gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);  in dwapb_get_reset()
644 	if (IS_ERR(gpio->rst))  in dwapb_get_reset()
645 		return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),  in dwapb_get_reset()
648 	err = reset_control_deassert(gpio->rst);  in dwapb_get_reset()
650 		dev_err(gpio->dev, "Cannot deassert reset lane\n");  in dwapb_get_reset()
654 	return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);  in dwapb_get_reset()
659 	struct dwapb_gpio *gpio = data;  in dwapb_disable_clks()  local
661 	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);  in dwapb_disable_clks()
664 static int dwapb_get_clks(struct dwapb_gpio *gpio)  in dwapb_get_clks()  argument
669 	gpio->clks[0].id = "bus";  in dwapb_get_clks()
670 	gpio->clks[1].id = "db";  in dwapb_get_clks()
671 	err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,  in dwapb_get_clks()
672 					 gpio->clks);  in dwapb_get_clks()
674 		return dev_err_probe(gpio->dev, err,  in dwapb_get_clks()
677 	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);  in dwapb_get_clks()
679 		dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");  in dwapb_get_clks()
683 	return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);  in dwapb_get_clks()
687 	{ .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
688 	{ .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
704 	struct dwapb_gpio *gpio;  in dwapb_gpio_probe()  local
707 	struct device *dev = &pdev->dev;  in dwapb_gpio_probe()
713 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);  in dwapb_gpio_probe()
714 	if (!gpio)  in dwapb_gpio_probe()
715 		return -ENOMEM;  in dwapb_gpio_probe()
717 	gpio->dev = &pdev->dev;  in dwapb_gpio_probe()
718 	gpio->nr_ports = pdata->nports;  in dwapb_gpio_probe()
720 	err = dwapb_get_reset(gpio);  in dwapb_gpio_probe()
724 	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,  in dwapb_gpio_probe()
725 				   sizeof(*gpio->ports), GFP_KERNEL);  in dwapb_gpio_probe()
726 	if (!gpio->ports)  in dwapb_gpio_probe()
727 		return -ENOMEM;  in dwapb_gpio_probe()
729 	gpio->regs = devm_platform_ioremap_resource(pdev, 0);  in dwapb_gpio_probe()
730 	if (IS_ERR(gpio->regs))  in dwapb_gpio_probe()
731 		return PTR_ERR(gpio->regs);  in dwapb_gpio_probe()
733 	err = dwapb_get_clks(gpio);  in dwapb_gpio_probe()
737 	gpio->flags = (uintptr_t)device_get_match_data(dev);  in dwapb_gpio_probe()
739 	for (i = 0; i < gpio->nr_ports; i++) {  in dwapb_gpio_probe()
740 		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);  in dwapb_gpio_probe()
745 	platform_set_drvdata(pdev, gpio);  in dwapb_gpio_probe()
753 	struct dwapb_gpio *gpio = dev_get_drvdata(dev);  in dwapb_gpio_suspend()  local
754 	struct gpio_chip *gc	= &gpio->ports[0].gc;  in dwapb_gpio_suspend()
758 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_gpio_suspend()
759 	for (i = 0; i < gpio->nr_ports; i++) {  in dwapb_gpio_suspend()
761 		unsigned int idx = gpio->ports[i].idx;  in dwapb_gpio_suspend()
762 		struct dwapb_context *ctx = gpio->ports[i].ctx;  in dwapb_gpio_suspend()
765 		ctx->dir = dwapb_read(gpio, offset);  in dwapb_gpio_suspend()
768 		ctx->data = dwapb_read(gpio, offset);  in dwapb_gpio_suspend()
771 		ctx->ext = dwapb_read(gpio, offset);  in dwapb_gpio_suspend()
775 			ctx->int_mask	= dwapb_read(gpio, GPIO_INTMASK);  in dwapb_gpio_suspend()
776 			ctx->int_en	= dwapb_read(gpio, GPIO_INTEN);  in dwapb_gpio_suspend()
777 			ctx->int_pol	= dwapb_read(gpio, GPIO_INT_POLARITY);  in dwapb_gpio_suspend()
778 			ctx->int_type	= dwapb_read(gpio, GPIO_INTTYPE_LEVEL);  in dwapb_gpio_suspend()
779 			ctx->int_deb	= dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);  in dwapb_gpio_suspend()
782 			dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);  in dwapb_gpio_suspend()
785 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_gpio_suspend()
787 	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);  in dwapb_gpio_suspend()
794 	struct dwapb_gpio *gpio = dev_get_drvdata(dev);  in dwapb_gpio_resume()  local
795 	struct gpio_chip *gc	= &gpio->ports[0].gc;  in dwapb_gpio_resume()
799 	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);  in dwapb_gpio_resume()
801 		dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");  in dwapb_gpio_resume()
805 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);  in dwapb_gpio_resume()
806 	for (i = 0; i < gpio->nr_ports; i++) {  in dwapb_gpio_resume()
808 		unsigned int idx = gpio->ports[i].idx;  in dwapb_gpio_resume()
809 		struct dwapb_context *ctx = gpio->ports[i].ctx;  in dwapb_gpio_resume()
812 		dwapb_write(gpio, offset, ctx->data);  in dwapb_gpio_resume()
815 		dwapb_write(gpio, offset, ctx->dir);  in dwapb_gpio_resume()
818 		dwapb_write(gpio, offset, ctx->ext);  in dwapb_gpio_resume()
822 			dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);  in dwapb_gpio_resume()
823 			dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);  in dwapb_gpio_resume()
824 			dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);  in dwapb_gpio_resume()
825 			dwapb_write(gpio, GPIO_INTEN, ctx->int_en);  in dwapb_gpio_resume()
826 			dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);  in dwapb_gpio_resume()
829 			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);  in dwapb_gpio_resume()
832 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);  in dwapb_gpio_resume()
855 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");