Lines Matching refs:g

73 	struct davinci_gpio_regs __iomem *g;  in irq2regs()  local
75 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); in irq2regs()
77 return g; in irq2regs()
89 struct davinci_gpio_regs __iomem *g; in __davinci_direction() local
95 g = d->regs[bank]; in __davinci_direction()
97 temp = readl_relaxed(&g->dir); in __davinci_direction()
100 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
104 writel_relaxed(temp, &g->dir); in __davinci_direction()
131 struct davinci_gpio_regs __iomem *g; in davinci_gpio_get() local
134 g = d->regs[bank]; in davinci_gpio_get()
136 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
146 struct davinci_gpio_regs __iomem *g; in davinci_gpio_set() local
149 g = d->regs[bank]; in davinci_gpio_set()
152 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
256 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_mask() local
259 writel_relaxed(mask, &g->clr_falling); in gpio_irq_mask()
260 writel_relaxed(mask, &g->clr_rising); in gpio_irq_mask()
265 struct davinci_gpio_regs __iomem *g = irq2regs(d); in gpio_irq_unmask() local
274 writel_relaxed(mask, &g->set_falling); in gpio_irq_unmask()
276 writel_relaxed(mask, &g->set_rising); in gpio_irq_unmask()
297 struct davinci_gpio_regs __iomem *g; in gpio_irq_handler() local
305 g = irqdata->regs; in gpio_irq_handler()
320 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
323 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
369 struct davinci_gpio_regs __iomem *g; in gpio_irq_type_unbanked() local
373 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
387 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
389 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
400 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; in davinci_gpio_irq_map() local
405 irq_set_chip_data(irq, (__force void *)g); in davinci_gpio_irq_map()
452 struct davinci_gpio_regs __iomem *g; in davinci_gpio_irq_setup() local
516 g = chips->regs[0]; in davinci_gpio_irq_setup()
517 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
518 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
540 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
541 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
542 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
556 irqdata->regs = g; in davinci_gpio_irq_setup()
579 struct davinci_gpio_regs __iomem *g; in davinci_gpio_save_context() local
588 g = chips->regs[bank]; in davinci_gpio_save_context()
590 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
591 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
592 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
593 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
597 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
603 struct davinci_gpio_regs __iomem *g; in davinci_gpio_restore_context() local
614 g = chips->regs[bank]; in davinci_gpio_restore_context()
616 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
617 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
618 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
619 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
620 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
621 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
622 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
623 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()