Lines Matching +full:keystone +full:- +full:irq
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
15 #include <linux/irq.h>
41 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
73 /*--------------------------------------------------------------------------*/
86 g = d->regs[bank]; in __davinci_direction()
87 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
88 temp = readl_relaxed(&g->dir); in __davinci_direction()
91 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
95 writel_relaxed(temp, &g->dir); in __davinci_direction()
96 spin_unlock_irqrestore(&d->lock, flags); in __davinci_direction()
125 g = d->regs[bank]; in davinci_gpio_get()
127 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); in davinci_gpio_get()
140 g = d->regs[bank]; in davinci_gpio_set()
143 value ? &g->set_data : &g->clr_data); in davinci_gpio_set()
153 struct device *dev = &pdev->dev; in davinci_gpio_probe()
157 * and "ngpio" is one more than the largest zero-based in davinci_gpio_probe()
164 return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n"); in davinci_gpio_probe()
171 ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked", in davinci_gpio_probe()
183 return -EINVAL; in davinci_gpio_probe()
188 return -ENOMEM; in davinci_gpio_probe()
195 chips->irqs[i] = platform_get_irq(pdev, i); in davinci_gpio_probe()
196 if (chips->irqs[i] < 0) in davinci_gpio_probe()
197 return chips->irqs[i]; in davinci_gpio_probe()
200 chips->chip.label = dev_name(dev); in davinci_gpio_probe()
202 chips->chip.direction_input = davinci_direction_in; in davinci_gpio_probe()
203 chips->chip.get = davinci_gpio_get; in davinci_gpio_probe()
204 chips->chip.direction_output = davinci_direction_out; in davinci_gpio_probe()
205 chips->chip.set = davinci_gpio_set; in davinci_gpio_probe()
207 chips->chip.ngpio = ngpio; in davinci_gpio_probe()
208 chips->chip.base = -1; in davinci_gpio_probe()
211 chips->chip.parent = dev; in davinci_gpio_probe()
212 chips->chip.request = gpiochip_generic_request; in davinci_gpio_probe()
213 chips->chip.free = gpiochip_generic_free; in davinci_gpio_probe()
215 spin_lock_init(&chips->lock); in davinci_gpio_probe()
217 chips->gpio_unbanked = gpio_unbanked; in davinci_gpio_probe()
221 chips->regs[bank] = gpio_base + offset_array[bank]; in davinci_gpio_probe()
223 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); in davinci_gpio_probe()
235 /*--------------------------------------------------------------------------*/
241 * to their GPIOBNK0 irq, with a bit less overhead.
243 * All those INTC hookups (direct, plus several IRQ banks) can also
251 struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32]; in gpio_irq_mask()
254 writel_relaxed(mask, &g->clr_falling); in gpio_irq_mask()
255 writel_relaxed(mask, &g->clr_rising); in gpio_irq_mask()
257 gpiochip_disable_irq(&chips->chip, hwirq); in gpio_irq_mask()
264 struct davinci_gpio_regs __iomem *g = chips->regs[hwirq / 32]; in gpio_irq_unmask()
268 gpiochip_enable_irq(&chips->chip, hwirq); in gpio_irq_unmask()
275 writel_relaxed(mask, &g->set_falling); in gpio_irq_unmask()
277 writel_relaxed(mask, &g->set_rising); in gpio_irq_unmask()
283 return -EINVAL; in gpio_irq_type()
306 bank_num = irqdata->bank_num; in gpio_irq_handler()
307 g = irqdata->regs; in gpio_irq_handler()
308 d = irqdata->chip; in gpio_irq_handler()
314 /* temporarily mask (level sensitive) parent IRQ */ in gpio_irq_handler()
322 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
325 writel_relaxed(status, &g->intstat); in gpio_irq_handler()
337 generic_handle_domain_irq(d->irq_domain, hw_irq); in gpio_irq_handler()
341 /* now it may re-trigger */ in gpio_irq_handler()
348 if (d->irq_domain) in gpio_to_irq_banked()
349 return irq_create_mapping(d->irq_domain, offset); in gpio_to_irq_banked()
351 return -ENXIO; in gpio_to_irq_banked()
360 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). in gpio_to_irq_unbanked()
362 if (offset < d->gpio_unbanked) in gpio_to_irq_unbanked()
363 return d->irqs[offset]; in gpio_to_irq_unbanked()
365 return -ENODEV; in gpio_to_irq_unbanked()
375 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; in gpio_irq_type_unbanked()
377 if (data->irq == d->irqs[i]) in gpio_irq_type_unbanked()
381 return -EINVAL; in gpio_irq_type_unbanked()
386 return -EINVAL; in gpio_irq_type_unbanked()
389 ? &g->set_falling : &g->clr_falling); in gpio_irq_type_unbanked()
391 ? &g->set_rising : &g->clr_rising); in gpio_irq_type_unbanked()
397 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, in davinci_gpio_irq_map() argument
401 (struct davinci_gpio_controller *)d->host_data; in davinci_gpio_irq_map()
403 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, in davinci_gpio_irq_map()
405 irq_set_irq_type(irq, IRQ_TYPE_NONE); in davinci_gpio_irq_map()
406 irq_set_chip_data(irq, (__force void *)chips); in davinci_gpio_irq_map()
407 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); in davinci_gpio_irq_map()
417 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) in davinci_gpio_get_irq_chip() argument
421 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); in davinci_gpio_get_irq_chip()
426 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) in keystone_gpio_get_irq_chip() argument
430 gpio_unbanked = *irq_get_chip(irq); in keystone_gpio_get_irq_chip()
447 int irq; in davinci_gpio_irq_setup() local
451 struct device *dev = &pdev->dev; in davinci_gpio_irq_setup()
463 if (dev->of_node) in davinci_gpio_irq_setup()
466 ngpio = chips->chip.ngpio; in davinci_gpio_irq_setup()
474 if (!chips->gpio_unbanked) { in davinci_gpio_irq_setup()
475 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); in davinci_gpio_irq_setup()
476 if (irq < 0) { in davinci_gpio_irq_setup()
477 dev_err(dev, "Couldn't allocate IRQ numbers\n"); in davinci_gpio_irq_setup()
478 return irq; in davinci_gpio_irq_setup()
481 irq_domain = irq_domain_create_legacy(dev_fwnode(dev), ngpio, irq, 0, in davinci_gpio_irq_setup()
484 dev_err(dev, "Couldn't register an IRQ domain\n"); in davinci_gpio_irq_setup()
485 return -ENODEV; in davinci_gpio_irq_setup()
495 chips->chip.to_irq = gpio_to_irq_banked; in davinci_gpio_irq_setup()
496 chips->irq_domain = irq_domain; in davinci_gpio_irq_setup()
501 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. in davinci_gpio_irq_setup()
503 if (chips->gpio_unbanked) { in davinci_gpio_irq_setup()
505 chips->chip.to_irq = gpio_to_irq_unbanked; in davinci_gpio_irq_setup()
507 binten = GENMASK(chips->gpio_unbanked / 16, 0); in davinci_gpio_irq_setup()
510 irq = chips->irqs[0]; in davinci_gpio_irq_setup()
511 irq_chip = gpio_get_irq_chip(irq); in davinci_gpio_irq_setup()
512 irq_chip->name = "GPIO-AINTC"; in davinci_gpio_irq_setup()
513 irq_chip->irq_set_type = gpio_irq_type_unbanked; in davinci_gpio_irq_setup()
516 g = chips->regs[0]; in davinci_gpio_irq_setup()
517 writel_relaxed(~0, &g->set_falling); in davinci_gpio_irq_setup()
518 writel_relaxed(~0, &g->set_rising); in davinci_gpio_irq_setup()
521 for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) { in davinci_gpio_irq_setup()
522 irq_set_chip(chips->irqs[gpio], irq_chip); in davinci_gpio_irq_setup()
523 irq_set_handler_data(chips->irqs[gpio], chips); in davinci_gpio_irq_setup()
524 irq_set_status_flags(chips->irqs[gpio], in davinci_gpio_irq_setup()
540 g = chips->regs[bank / 2]; in davinci_gpio_irq_setup()
541 writel_relaxed(~0, &g->clr_falling); in davinci_gpio_irq_setup()
542 writel_relaxed(~0, &g->clr_rising); in davinci_gpio_irq_setup()
545 * Each chip handles 32 gpios, and each irq bank consists of 16 in davinci_gpio_irq_setup()
546 * gpio irqs. Pass the irq bank's corresponding controller to in davinci_gpio_irq_setup()
547 * the chained irq handler. in davinci_gpio_irq_setup()
549 irqdata = devm_kzalloc(&pdev->dev, in davinci_gpio_irq_setup()
554 return -ENOMEM; in davinci_gpio_irq_setup()
556 irqdata->regs = g; in davinci_gpio_irq_setup()
557 irqdata->bank_num = bank; in davinci_gpio_irq_setup()
558 irqdata->chip = chips; in davinci_gpio_irq_setup()
560 irq_set_chained_handler_and_data(chips->irqs[bank], in davinci_gpio_irq_setup()
568 * BINTEN -- per-bank interrupt enable. genirq would also let these in davinci_gpio_irq_setup()
584 base = chips->regs[0] - offset_array[0]; in davinci_gpio_save_context()
585 chips->binten_context = readl_relaxed(base + BINTEN); in davinci_gpio_save_context()
588 g = chips->regs[bank]; in davinci_gpio_save_context()
589 context = &chips->context[bank]; in davinci_gpio_save_context()
590 context->dir = readl_relaxed(&g->dir); in davinci_gpio_save_context()
591 context->set_data = readl_relaxed(&g->set_data); in davinci_gpio_save_context()
592 context->set_rising = readl_relaxed(&g->set_rising); in davinci_gpio_save_context()
593 context->set_falling = readl_relaxed(&g->set_falling); in davinci_gpio_save_context()
597 writel_relaxed(GENMASK(31, 0), &g->intstat); in davinci_gpio_save_context()
608 base = chips->regs[0] - offset_array[0]; in davinci_gpio_restore_context()
610 if (readl_relaxed(base + BINTEN) != chips->binten_context) in davinci_gpio_restore_context()
611 writel_relaxed(chips->binten_context, base + BINTEN); in davinci_gpio_restore_context()
614 g = chips->regs[bank]; in davinci_gpio_restore_context()
615 context = &chips->context[bank]; in davinci_gpio_restore_context()
616 if (readl_relaxed(&g->dir) != context->dir) in davinci_gpio_restore_context()
617 writel_relaxed(context->dir, &g->dir); in davinci_gpio_restore_context()
618 if (readl_relaxed(&g->set_data) != context->set_data) in davinci_gpio_restore_context()
619 writel_relaxed(context->set_data, &g->set_data); in davinci_gpio_restore_context()
620 if (readl_relaxed(&g->set_rising) != context->set_rising) in davinci_gpio_restore_context()
621 writel_relaxed(context->set_rising, &g->set_rising); in davinci_gpio_restore_context()
622 if (readl_relaxed(&g->set_falling) != context->set_falling) in davinci_gpio_restore_context()
623 writel_relaxed(context->set_falling, &g->set_falling); in davinci_gpio_restore_context()
630 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); in davinci_gpio_suspend()
640 u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32); in davinci_gpio_resume()
651 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
652 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
653 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
686 MODULE_ALIAS("platform:gpio-davinci");