1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright (c) 2006-2007 David Brownell
43 #define BINTEN	0x8 /* GPIO Interrupt Per-Bank Enable Register */
82 /*--------------------------------------------------------------------------*/
95 	g = d->regs[bank];  in __davinci_direction()
96 	spin_lock_irqsave(&d->lock, flags);  in __davinci_direction()
97 	temp = readl_relaxed(&g->dir);  in __davinci_direction()
100 		writel_relaxed(mask, value ? &g->set_data : &g->clr_data);  in __davinci_direction()
104 	writel_relaxed(temp, &g->dir);  in __davinci_direction()
105 	spin_unlock_irqrestore(&d->lock, flags);  in __davinci_direction()
134 	g = d->regs[bank];  in davinci_gpio_get()
136 	return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));  in davinci_gpio_get()
149 	g = d->regs[bank];  in davinci_gpio_set()
152 		       value ? &g->set_data : &g->clr_data);  in davinci_gpio_set()
160 	struct device *dev = &pdev->dev;  in davinci_gpio_probe()
164 	 * and "ngpio" is one more than the largest zero-based  in davinci_gpio_probe()
169 		return dev_err_probe(dev, ret, "Failed to get the number of GPIOs\n");  in davinci_gpio_probe()
171 		return dev_err_probe(dev, -EINVAL, "How many GPIOs?\n");  in davinci_gpio_probe()
175 	 * interrupts is equal to number of gpios else all are banked so  in davinci_gpio_probe()
176 	 * number of interrupts is equal to number of banks(each with 16 gpios)  in davinci_gpio_probe()
178 	ret = device_property_read_u32(dev, "ti,davinci-gpio-unbanked",  in davinci_gpio_probe()
181 		return dev_err_probe(dev, ret, "Failed to get the unbanked GPIOs property\n");  in davinci_gpio_probe()
190 		return -EINVAL;  in davinci_gpio_probe()
195 		return -ENOMEM;  in davinci_gpio_probe()
202 		chips->irqs[i] = platform_get_irq(pdev, i);  in davinci_gpio_probe()
203 		if (chips->irqs[i] < 0)  in davinci_gpio_probe()
204 			return chips->irqs[i];  in davinci_gpio_probe()
207 	chips->chip.label = dev_name(dev);  in davinci_gpio_probe()
209 	chips->chip.direction_input = davinci_direction_in;  in davinci_gpio_probe()
210 	chips->chip.get = davinci_gpio_get;  in davinci_gpio_probe()
211 	chips->chip.direction_output = davinci_direction_out;  in davinci_gpio_probe()
212 	chips->chip.set = davinci_gpio_set;  in davinci_gpio_probe()
214 	chips->chip.ngpio = ngpio;  in davinci_gpio_probe()
215 	chips->chip.base = -1;  in davinci_gpio_probe()
218 	chips->chip.parent = dev;  in davinci_gpio_probe()
219 	chips->chip.request = gpiochip_generic_request;  in davinci_gpio_probe()
220 	chips->chip.free = gpiochip_generic_free;  in davinci_gpio_probe()
222 	spin_lock_init(&chips->lock);  in davinci_gpio_probe()
224 	chips->gpio_unbanked = gpio_unbanked;  in davinci_gpio_probe()
228 		chips->regs[bank] = gpio_base + offset_array[bank];  in davinci_gpio_probe()
230 	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);  in davinci_gpio_probe()
242 /*--------------------------------------------------------------------------*/
247  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
259 	writel_relaxed(mask, &g->clr_falling);  in gpio_irq_mask()
260 	writel_relaxed(mask, &g->clr_rising);  in gpio_irq_mask()
274 		writel_relaxed(mask, &g->set_falling);  in gpio_irq_unmask()
276 		writel_relaxed(mask, &g->set_rising);  in gpio_irq_unmask()
282 		return -EINVAL;  in gpio_irq_type()
304 	bank_num = irqdata->bank_num;  in gpio_irq_handler()
305 	g = irqdata->regs;  in gpio_irq_handler()
306 	d = irqdata->chip;  in gpio_irq_handler()
320 		status = readl_relaxed(&g->intstat) & mask;  in gpio_irq_handler()
323 		writel_relaxed(status, &g->intstat);  in gpio_irq_handler()
330 			/* Max number of gpios per controller is 144 so  in gpio_irq_handler()
335 			generic_handle_domain_irq(d->irq_domain, hw_irq);  in gpio_irq_handler()
339 	/* now it may re-trigger */  in gpio_irq_handler()
346 	if (d->irq_domain)  in gpio_to_irq_banked()
347 		return irq_create_mapping(d->irq_domain, offset);  in gpio_to_irq_banked()
349 		return -ENXIO;  in gpio_to_irq_banked()
357 	 * NOTE:  we assume for now that only irqs in the first gpio_chip  in gpio_to_irq_unbanked()
358 	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).  in gpio_to_irq_unbanked()
360 	if (offset < d->gpio_unbanked)  in gpio_to_irq_unbanked()
361 		return d->irqs[offset];  in gpio_to_irq_unbanked()
363 		return -ENODEV;  in gpio_to_irq_unbanked()
366 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)  in gpio_irq_type_unbanked()  argument
372 	d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);  in gpio_irq_type_unbanked()
373 	g = (struct davinci_gpio_regs __iomem *)d->regs[0];  in gpio_irq_type_unbanked()
375 		if (data->irq == d->irqs[i])  in gpio_irq_type_unbanked()
379 		return -EINVAL;  in gpio_irq_type_unbanked()
384 		return -EINVAL;  in gpio_irq_type_unbanked()
387 		     ? &g->set_falling : &g->clr_falling);  in gpio_irq_type_unbanked()
389 		     ? &g->set_rising : &g->clr_rising);  in gpio_irq_type_unbanked()
399 				(struct davinci_gpio_controller *)d->host_data;  in davinci_gpio_irq_map()
400 	struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];  in davinci_gpio_irq_map()
438  * calls ... so if no gpios are wakeup events the clock can be disabled,
450 	struct device *dev = &pdev->dev;  in davinci_gpio_irq_setup()
462 	if (dev->of_node)  in davinci_gpio_irq_setup()
465 	ngpio = chips->chip.ngpio;  in davinci_gpio_irq_setup()
473 	if (!chips->gpio_unbanked) {  in davinci_gpio_irq_setup()
474 		irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);  in davinci_gpio_irq_setup()
480 		irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,  in davinci_gpio_irq_setup()
485 			return -ENODEV;  in davinci_gpio_irq_setup()
491 	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct  in davinci_gpio_irq_setup()
495 	chips->chip.to_irq = gpio_to_irq_banked;  in davinci_gpio_irq_setup()
496 	chips->irq_domain = irq_domain;  in davinci_gpio_irq_setup()
499 	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO  in davinci_gpio_irq_setup()
501 	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.  in davinci_gpio_irq_setup()
503 	if (chips->gpio_unbanked) {  in davinci_gpio_irq_setup()
505 		chips->chip.to_irq = gpio_to_irq_unbanked;  in davinci_gpio_irq_setup()
507 		binten = GENMASK(chips->gpio_unbanked / 16, 0);  in davinci_gpio_irq_setup()
510 		irq = chips->irqs[0];  in davinci_gpio_irq_setup()
512 		irq_chip->name = "GPIO-AINTC";  in davinci_gpio_irq_setup()
513 		irq_chip->irq_set_type = gpio_irq_type_unbanked;  in davinci_gpio_irq_setup()
516 		g = chips->regs[0];  in davinci_gpio_irq_setup()
517 		writel_relaxed(~0, &g->set_falling);  in davinci_gpio_irq_setup()
518 		writel_relaxed(~0, &g->set_rising);  in davinci_gpio_irq_setup()
521 		for (gpio = 0; gpio < chips->gpio_unbanked; gpio++) {  in davinci_gpio_irq_setup()
522 			irq_set_chip(chips->irqs[gpio], irq_chip);  in davinci_gpio_irq_setup()
523 			irq_set_handler_data(chips->irqs[gpio], chips);  in davinci_gpio_irq_setup()
524 			irq_set_status_flags(chips->irqs[gpio],  in davinci_gpio_irq_setup()
537 		 * There are register sets for 32 GPIOs. 2 banks of 16  in davinci_gpio_irq_setup()
538 		 * GPIOs are covered by each set of registers hence divide by 2  in davinci_gpio_irq_setup()
540 		g = chips->regs[bank / 2];  in davinci_gpio_irq_setup()
541 		writel_relaxed(~0, &g->clr_falling);  in davinci_gpio_irq_setup()
542 		writel_relaxed(~0, &g->clr_rising);  in davinci_gpio_irq_setup()
545 		 * Each chip handles 32 gpios, and each irq bank consists of 16  in davinci_gpio_irq_setup()
549 		irqdata = devm_kzalloc(&pdev->dev,  in davinci_gpio_irq_setup()
554 			return -ENOMEM;  in davinci_gpio_irq_setup()
556 		irqdata->regs = g;  in davinci_gpio_irq_setup()
557 		irqdata->bank_num = bank;  in davinci_gpio_irq_setup()
558 		irqdata->chip = chips;  in davinci_gpio_irq_setup()
560 		irq_set_chained_handler_and_data(chips->irqs[bank],  in davinci_gpio_irq_setup()
568 	 * BINTEN -- per-bank interrupt enable. genirq would also let these  in davinci_gpio_irq_setup()
584 	base = chips->regs[0] - offset_array[0];  in davinci_gpio_save_context()
585 	chips->binten_context = readl_relaxed(base + BINTEN);  in davinci_gpio_save_context()
588 		g = chips->regs[bank];  in davinci_gpio_save_context()
589 		context = &chips->context[bank];  in davinci_gpio_save_context()
590 		context->dir = readl_relaxed(&g->dir);  in davinci_gpio_save_context()
591 		context->set_data = readl_relaxed(&g->set_data);  in davinci_gpio_save_context()
592 		context->set_rising = readl_relaxed(&g->set_rising);  in davinci_gpio_save_context()
593 		context->set_falling = readl_relaxed(&g->set_falling);  in davinci_gpio_save_context()
597 	writel_relaxed(GENMASK(31, 0), &g->intstat);  in davinci_gpio_save_context()
608 	base = chips->regs[0] - offset_array[0];  in davinci_gpio_restore_context()
610 	if (readl_relaxed(base + BINTEN) != chips->binten_context)  in davinci_gpio_restore_context()
611 		writel_relaxed(chips->binten_context, base + BINTEN);  in davinci_gpio_restore_context()
614 		g = chips->regs[bank];  in davinci_gpio_restore_context()
615 		context = &chips->context[bank];  in davinci_gpio_restore_context()
616 		if (readl_relaxed(&g->dir) != context->dir)  in davinci_gpio_restore_context()
617 			writel_relaxed(context->dir, &g->dir);  in davinci_gpio_restore_context()
618 		if (readl_relaxed(&g->set_data) != context->set_data)  in davinci_gpio_restore_context()
619 			writel_relaxed(context->set_data, &g->set_data);  in davinci_gpio_restore_context()
620 		if (readl_relaxed(&g->set_rising) != context->set_rising)  in davinci_gpio_restore_context()
621 			writel_relaxed(context->set_rising, &g->set_rising);  in davinci_gpio_restore_context()
622 		if (readl_relaxed(&g->set_falling) != context->set_falling)  in davinci_gpio_restore_context()
623 			writel_relaxed(context->set_falling, &g->set_falling);  in davinci_gpio_restore_context()
630 	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);  in davinci_gpio_suspend()
640 	u32 nbank = DIV_ROUND_UP(chips->chip.ngpio, 32);  in davinci_gpio_resume()
651 	{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
652 	{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
653 	{ .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
686 MODULE_ALIAS("platform:gpio-davinci");