Lines Matching +full:input +full:- +full:debounce

1 // SPDX-License-Identifier: GPL-2.0-or-later
33 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
34 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
35 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
56 u32 input; member
97 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
108 * Note: The "value" register returns the input value sampled on the
110 * that input goes through synchronizers, writing, then reading
122 * The debounce timers array is used to configure the debounce timer settings.Here’s how it works:
123 * Array Value: Indicates the offset for configuring the debounce timer.
124 * Array Index: Corresponds to the debounce setting register.
125 * The debounce timers array follows this pattern for configuring the debounce setting registers:
126 * Array Index 0: No debounce timer is set;
128 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0.
129 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00)
130 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1.
131 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04)
132 * Array Index 3: Debounce setting #2 is set to 1, and debounce setting #1 is set to 1.
133 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8)
261 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in aspeed_gpio_g4_bank_reg()
263 return gpio->base + bank->rdata_reg; in aspeed_gpio_g4_bank_reg()
265 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in aspeed_gpio_g4_bank_reg()
267 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in aspeed_gpio_g4_bank_reg()
269 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in aspeed_gpio_g4_bank_reg()
271 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in aspeed_gpio_g4_bank_reg()
273 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in aspeed_gpio_g4_bank_reg()
275 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in aspeed_gpio_g4_bank_reg()
277 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in aspeed_gpio_g4_bank_reg()
279 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in aspeed_gpio_g4_bank_reg()
281 return gpio->base + bank->tolerance_regs; in aspeed_gpio_g4_bank_reg()
283 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in aspeed_gpio_g4_bank_reg()
285 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in aspeed_gpio_g4_bank_reg()
337 return !(props->input || props->output); in is_bank_props_sentinel()
343 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
346 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
358 if (offset >= gpio->chip.ngpio) in have_gpio()
361 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
368 return !props || (props->input & GPIO_BIT(offset)); in have_input()
378 return !props || (props->output & GPIO_BIT(offset)); in have_output()
383 if (gpio->config->llops->privilege_ctrl) in aspeed_gpio_change_cmd_source()
384 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); in aspeed_gpio_change_cmd_source()
390 if (gpio->config->llops->copro_request) in aspeed_gpio_copro_request()
391 return gpio->config->llops->copro_request(gpio, offset); in aspeed_gpio_copro_request()
399 if (gpio->config->llops->copro_release) in aspeed_gpio_copro_release()
400 gpio->config->llops->copro_release(gpio, offset); in aspeed_gpio_copro_release()
405 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && in aspeed_gpio_support_copro()
406 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; in aspeed_gpio_support_copro()
413 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in aspeed_gpio_get()
421 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); in __aspeed_gpio_set()
423 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in __aspeed_gpio_set()
433 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
440 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
450 return -ENOTSUPP; in aspeed_gpio_dir_in()
452 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); in aspeed_gpio_dir_in()
459 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
472 return -ENOTSUPP; in aspeed_gpio_dir_out()
474 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
478 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); in aspeed_gpio_dir_out()
482 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
499 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
501 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); in aspeed_gpio_get_direction()
503 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
520 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
538 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
541 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); in aspeed_gpio_irq_ack()
545 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
561 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
563 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
566 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); in aspeed_gpio_irq_set_mask()
570 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
574 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
600 return -EINVAL; in aspeed_gpio_set_type()
620 return -EINVAL; in aspeed_gpio_set_type()
623 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
626 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); in aspeed_gpio_set_type()
627 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); in aspeed_gpio_set_type()
628 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); in aspeed_gpio_set_type()
632 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
649 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
651 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); in aspeed_gpio_irq_handler()
654 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
665 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
669 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask() local
672 for_each_clear_bit(offset, &input, 32) { in aspeed_init_irq_valid_mask()
673 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
675 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
692 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
695 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); in aspeed_gpio_reset_tolerance()
699 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
707 return -ENODEV; in aspeed_gpio_request()
724 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
726 return -ENOTSUPP; in usecs_to_cycles()
732 return -ERANGE; in usecs_to_cycles()
740 /* Call under gpio->lock */
744 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
746 offset, gpio->offset_timer[offset])) in register_allocated_timer()
747 return -EINVAL; in register_allocated_timer()
749 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
751 return -EPERM; in register_allocated_timer()
753 gpio->offset_timer[offset] = timer; in register_allocated_timer()
754 gpio->timer_users[timer]++; in register_allocated_timer()
759 /* Call under gpio->lock */
763 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
765 return -EINVAL; in unregister_allocated_timer()
767 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
769 gpio->offset_timer[offset])) in unregister_allocated_timer()
770 return -EINVAL; in unregister_allocated_timer()
772 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
773 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
778 /* Call under gpio->lock */
782 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
785 /* Call under gpio->lock */
789 /* Note: Debounce timer isn't under control of the command in configure_timer()
792 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); in configure_timer()
793 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); in configure_timer()
805 if (!gpio->clk) in enable_debounce()
806 return -EINVAL; in enable_debounce()
810 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
811 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
815 raw_spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
823 /* Try to find a timer already configured for the debounce period */ in enable_debounce()
824 for (i = 1; i < gpio->config->debounce_timers_num; i++) { in enable_debounce()
827 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
832 if (i == gpio->config->debounce_timers_num) { in enable_debounce()
836 * As there are no timers configured for the requested debounce in enable_debounce()
839 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
840 if (gpio->timer_users[j] == 0) in enable_debounce()
844 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
845 dev_warn(chip->parent, in enable_debounce()
846 "Debounce timers exhausted, cannot debounce for period %luus\n", in enable_debounce()
849 rc = -EPERM; in enable_debounce()
863 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
867 rc = -EINVAL; in enable_debounce()
875 raw_spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
886 raw_spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
892 raw_spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
903 return -ENOTSUPP; in set_debounce()
925 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
926 return -ENOTSUPP; in aspeed_gpio_set_config()
930 return -ENOTSUPP; in aspeed_gpio_set_config()
934 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
949 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
953 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
954 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
955 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
967 return -EOPNOTSUPP; in aspeed_gpio_copro_grab_gpio()
969 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
970 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
971 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
972 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
973 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
974 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
977 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
980 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
981 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
984 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
987 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
992 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
994 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
998 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1004 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1015 return -EOPNOTSUPP; in aspeed_gpio_copro_release_gpio()
1017 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1018 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1020 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1021 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1024 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1027 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1028 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1031 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1034 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1038 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1052 seq_puts(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1073 temp = gpio->dcache[GPIO_BANK(offset)]; in aspeed_g4_reg_bit_set()
1083 gpio->dcache[GPIO_BANK(offset)] = temp; in aspeed_g4_reg_bit_set()
1105 return -EOPNOTSUPP; in aspeed_g4_reg_bank_get()
1125 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { in aspeed_g4_privilege_init()
1135 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_request()
1137 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_request()
1139 if (!copro_ops->request_access) in aspeed_g4_copro_request()
1143 copro_ops->request_access(copro_data); in aspeed_g4_copro_request()
1149 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); in aspeed_g4_copro_request()
1156 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_release()
1158 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_release()
1160 if (!copro_ops->release_access) in aspeed_g4_copro_release()
1167 copro_ops->release_access(copro_data); in aspeed_g4_copro_release()
1184 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_set()
1199 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_get()
1215 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); in aspeed_g7_reg_bank_get()
1218 return -EOPNOTSUPP; in aspeed_g7_reg_bank_get()
1236 * { .input = 0xffffffff, .output = 0xffffffff }
1240 /* input output */
1242 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1247 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1258 /* input output */
1260 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1266 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1277 /* input output */
1300 /* input output */
1301 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1309 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1323 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1324 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1325 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1326 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1339 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1341 return -ENOMEM; in aspeed_gpio_probe()
1343 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1344 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1345 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1347 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1349 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1351 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1353 return -EINVAL; in aspeed_gpio_probe()
1355 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in aspeed_gpio_probe()
1356 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1357 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1359 gpio->clk = NULL; in aspeed_gpio_probe()
1362 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1364 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || in aspeed_gpio_probe()
1365 !gpio->config->llops->reg_bank_get) in aspeed_gpio_probe()
1366 return -EINVAL; in aspeed_gpio_probe()
1368 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1369 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1370 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1372 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1373 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1374 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1375 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1376 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1377 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1378 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1379 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1380 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1381 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1382 gpio->chip.base = -1; in aspeed_gpio_probe()
1384 if (gpio->config->require_dcache) { in aspeed_gpio_probe()
1386 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1387 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); in aspeed_gpio_probe()
1388 if (!gpio->dcache) in aspeed_gpio_probe()
1389 return -ENOMEM; in aspeed_gpio_probe()
1394 gpio->dcache[i] = in aspeed_gpio_probe()
1395 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); in aspeed_gpio_probe()
1398 if (gpio->config->llops->privilege_init) in aspeed_gpio_probe()
1399 gpio->config->llops->privilege_init(gpio); in aspeed_gpio_probe()
1405 gpio->irq = irq; in aspeed_gpio_probe()
1406 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1409 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1410 girq->num_parents = 1; in aspeed_gpio_probe()
1411 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); in aspeed_gpio_probe()
1412 if (!girq->parents) in aspeed_gpio_probe()
1413 return -ENOMEM; in aspeed_gpio_probe()
1414 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1415 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1416 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1417 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1419 gpio->offset_timer = in aspeed_gpio_probe()
1420 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1421 if (!gpio->offset_timer) in aspeed_gpio_probe()
1422 return -ENOMEM; in aspeed_gpio_probe()
1424 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()