Lines Matching +full:gpio +full:-
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
50 * represents disabled debouncing for the GPIO. Any other value for an element
85 * line even when the GPIO is configured as an output. Since
210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() argument
216 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
218 return gpio->base + bank->rdata_reg; in bank_reg()
220 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
228 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
230 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
232 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in bank_reg()
234 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in bank_reg()
236 return gpio->base + bank->tolerance_regs; in bank_reg()
238 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in bank_reg()
240 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in bank_reg()
263 return !(props->input || props->output); in is_bank_props_sentinel()
267 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
269 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
272 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
280 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
282 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
286 return bank->names[group][0] != '\0' && in have_gpio()
287 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
290 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
292 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_input()
294 return !props || (props->input & GPIO_BIT(offset)); in have_input()
300 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) in have_output() argument
302 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_output()
304 return !props || (props->output & GPIO_BIT(offset)); in have_output()
307 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, in aspeed_gpio_change_cmd_source() argument
311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); in aspeed_gpio_change_cmd_source()
312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); in aspeed_gpio_change_cmd_source()
339 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, in aspeed_gpio_copro_request() argument
344 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_request()
346 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_request()
348 if (!copro_ops->request_access) in aspeed_gpio_copro_request()
352 copro_ops->request_access(copro_data); in aspeed_gpio_copro_request()
355 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); in aspeed_gpio_copro_request()
358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
363 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, in aspeed_gpio_copro_release() argument
368 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_gpio_copro_release()
370 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_gpio_copro_release()
372 if (!copro_ops->release_access) in aspeed_gpio_copro_release()
376 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, in aspeed_gpio_copro_release()
380 copro_ops->release_access(copro_data); in aspeed_gpio_copro_release()
385 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get() local
388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
394 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in __aspeed_gpio_set() local
399 addr = bank_reg(gpio, bank, reg_val); in __aspeed_gpio_set()
400 reg = gpio->dcache[GPIO_BANK(offset)]; in __aspeed_gpio_set()
406 gpio->dcache[GPIO_BANK(offset)] = reg; in __aspeed_gpio_set()
416 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_set() local
420 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
421 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set()
426 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set()
427 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
432 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_in() local
434 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_in()
439 if (!have_input(gpio, offset)) in aspeed_gpio_dir_in()
440 return -ENOTSUPP; in aspeed_gpio_dir_in()
442 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
447 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_in()
450 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_in()
452 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
460 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_out() local
462 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_out()
467 if (!have_output(gpio, offset)) in aspeed_gpio_dir_out()
468 return -ENOTSUPP; in aspeed_gpio_dir_out()
470 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
475 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_out()
480 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_out()
481 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
488 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get_direction() local
493 if (!have_input(gpio, offset)) in aspeed_gpio_get_direction()
496 if (!have_output(gpio, offset)) in aspeed_gpio_get_direction()
499 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
501 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
503 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
509 struct aspeed_gpio **gpio, in irqd_to_aspeed_gpio_data() argument
521 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
523 *gpio = internal; in irqd_to_aspeed_gpio_data()
533 struct aspeed_gpio *gpio; in aspeed_gpio_irq_ack() local
540 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_ack()
544 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_gpio_irq_ack()
546 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
547 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_ack()
552 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_ack()
553 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
559 struct aspeed_gpio *gpio; in aspeed_gpio_irq_set_mask() local
566 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_set_mask()
570 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_gpio_irq_set_mask()
574 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
576 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
577 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_set_mask()
587 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_set_mask()
588 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
592 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
613 struct aspeed_gpio *gpio; in aspeed_gpio_set_type() local
619 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_set_type()
621 return -EINVAL; in aspeed_gpio_set_type()
641 return -EINVAL; in aspeed_gpio_set_type()
644 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
645 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set_type()
647 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_gpio_set_type()
652 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_gpio_set_type()
657 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_gpio_set_type()
663 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set_type()
664 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
678 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_irq_handler() local
682 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
689 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
699 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_init_irq_valid_mask() local
700 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
704 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask()
706 /* Pretty crummy approach, but similar to GPIO core */ in aspeed_init_irq_valid_mask()
708 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
710 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
723 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_reset_tolerance() local
729 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); in aspeed_gpio_reset_tolerance()
731 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
732 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_reset_tolerance()
744 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_reset_tolerance()
745 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
753 return -ENODEV; in aspeed_gpio_request()
763 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, in usecs_to_cycles() argument
770 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
772 return -ENOTSUPP; in usecs_to_cycles()
778 return -ERANGE; in usecs_to_cycles()
786 /* Call under gpio->lock */
787 static int register_allocated_timer(struct aspeed_gpio *gpio, in register_allocated_timer() argument
790 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
792 offset, gpio->offset_timer[offset])) in register_allocated_timer()
793 return -EINVAL; in register_allocated_timer()
795 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
797 return -EPERM; in register_allocated_timer()
799 gpio->offset_timer[offset] = timer; in register_allocated_timer()
800 gpio->timer_users[timer]++; in register_allocated_timer()
805 /* Call under gpio->lock */
806 static int unregister_allocated_timer(struct aspeed_gpio *gpio, in unregister_allocated_timer() argument
809 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
811 return -EINVAL; in unregister_allocated_timer()
813 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
815 gpio->offset_timer[offset])) in unregister_allocated_timer()
816 return -EINVAL; in unregister_allocated_timer()
818 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
819 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
824 /* Call under gpio->lock */
825 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, in timer_allocation_registered() argument
828 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
831 /* Call under gpio->lock */
832 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, in configure_timer() argument
843 addr = bank_reg(gpio, bank, reg_debounce_sel1); in configure_timer()
847 addr = bank_reg(gpio, bank, reg_debounce_sel2); in configure_timer()
855 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in enable_debounce() local
861 if (!gpio->clk) in enable_debounce()
862 return -EINVAL; in enable_debounce()
864 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); in enable_debounce()
866 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
867 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
871 raw_spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
873 if (timer_allocation_registered(gpio, offset)) { in enable_debounce()
874 rc = unregister_allocated_timer(gpio, offset); in enable_debounce()
883 cycles = ioread32(gpio->base + debounce_timers[i]); in enable_debounce()
895 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
896 if (gpio->timer_users[j] == 0) in enable_debounce()
900 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
901 dev_warn(chip->parent, in enable_debounce()
905 rc = -EPERM; in enable_debounce()
913 configure_timer(gpio, offset, 0); in enable_debounce()
919 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); in enable_debounce()
923 rc = -EINVAL; in enable_debounce()
927 register_allocated_timer(gpio, offset, i); in enable_debounce()
928 configure_timer(gpio, offset, i); in enable_debounce()
931 raw_spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
938 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in disable_debounce() local
942 raw_spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
944 rc = unregister_allocated_timer(gpio, offset); in disable_debounce()
946 configure_timer(gpio, offset, 0); in disable_debounce()
948 raw_spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
956 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in set_debounce() local
958 if (!have_debounce(gpio, offset)) in set_debounce()
959 return -ENOTSUPP; in set_debounce()
981 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
982 return -ENOTSUPP; in aspeed_gpio_set_config()
986 return -ENOTSUPP; in aspeed_gpio_set_config()
990 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
991 * the coprocessor for shared GPIO banks
1005 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
1008 * @desc: The GPIO to be marked
1009 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
1010 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
1011 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1017 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_grab_gpio() local
1022 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1023 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
1024 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
1025 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
1026 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
1027 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
1030 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1033 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
1034 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
1037 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
1040 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
1041 aspeed_gpio_change_cmd_source(gpio, bank, bindex, in aspeed_gpio_copro_grab_gpio()
1045 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
1047 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
1051 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1057 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1058 * @desc: The GPIO to be marked
1063 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_release_gpio() local
1068 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1069 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1071 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1072 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1075 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1078 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1079 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1082 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1085 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1086 aspeed_gpio_change_cmd_source(gpio, bank, bindex, in aspeed_gpio_copro_release_gpio()
1089 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1097 struct aspeed_gpio *gpio; in aspeed_gpio_irq_print_chip() local
1101 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); in aspeed_gpio_irq_print_chip()
1105 seq_printf(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1128 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1133 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1139 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1145 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1165 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1166 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1167 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1176 struct aspeed_gpio *gpio; in aspeed_gpio_probe() local
1180 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1181 if (!gpio) in aspeed_gpio_probe()
1182 return -ENOMEM; in aspeed_gpio_probe()
1184 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1185 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1186 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1188 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1190 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1192 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1194 return -EINVAL; in aspeed_gpio_probe()
1196 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in aspeed_gpio_probe()
1197 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1198 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1200 gpio->clk = NULL; in aspeed_gpio_probe()
1203 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1205 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1206 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1207 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1209 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1210 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1211 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1212 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1213 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1214 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1215 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1216 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1217 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1218 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1219 gpio->chip.base = -1; in aspeed_gpio_probe()
1222 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1223 gpio->dcache = devm_kcalloc(&pdev->dev, in aspeed_gpio_probe()
1225 if (!gpio->dcache) in aspeed_gpio_probe()
1226 return -ENOMEM; in aspeed_gpio_probe()
1234 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); in aspeed_gpio_probe()
1235 gpio->dcache[i] = ioread32(addr); in aspeed_gpio_probe()
1236 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1237 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1238 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1239 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); in aspeed_gpio_probe()
1246 gpio->irq = irq; in aspeed_gpio_probe()
1247 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1250 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1251 girq->num_parents = 1; in aspeed_gpio_probe()
1252 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); in aspeed_gpio_probe()
1253 if (!girq->parents) in aspeed_gpio_probe()
1254 return -ENOMEM; in aspeed_gpio_probe()
1255 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1256 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1257 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1258 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1260 gpio->offset_timer = in aspeed_gpio_probe()
1261 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1262 if (!gpio->offset_timer) in aspeed_gpio_probe()
1263 return -ENOMEM; in aspeed_gpio_probe()
1265 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()
1281 MODULE_DESCRIPTION("Aspeed GPIO Driver");